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两侧同时换到之前的修订记录 前一修订版
pwm_awg [2021/03/08 17:50]
gongyusu [FPGA代码] 		pwm_awg [2021/03/08 17:57] (当前版本)
gongyusu
行 32: 行 32:
 <code verilog> <code verilog>
 wire   ​ [23:​0] next_phase;​ wire   ​ [23:​0] next_phase;​
-wire   ​ [7:​0] ​     ​phase;+wire   ​ [7:​0] ​ phase;
 reg    [23:0] accumulator;​ reg    [23:0] accumulator;​
  
-assign next_phase = 24'​H002222 + accumulator;​+assign next_phase = 24'​H002222 + accumulator; ​  // set frequency = 24'​H002222 / 2^24 * clock, if PLL not used, clock = 12MHz, output frequency = 6.25KHz
  
-always @(posedge clk_hs) ​ +always @(posedge clk_hs) accumulator <= #1 next_phase;
-      ​accumulator <= #1 next_phase;+
  
-assign phase = accumulator[23:​16]; ​   // phase is the high 8 bits+assign phase = accumulator[23:​16]; ​   // phase is the high 8 bits as address of the look up table
  
-wire [9:0] sine_data;+wire [9:0] sine_data; ​                  // sine table is 8 bit wide, 10bit resolution.
  
 lookup_tables u_lookup_tables(phase,​ sine_data); lookup_tables u_lookup_tables(phase,​ sine_data);
行 51: 行 50:
 <code verilog> <code verilog>
 module lookup_tables(phase,​ sin_out); module lookup_tables(phase,​ sin_out);
-input  [7:0] phase;+input  [7:0] phase; ​   //​sine table is 8bits wide, 10 bits resolution
 output [9:0] sin_out; output [9:0] sin_out;