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--- pwm_awg [2021/02/25 19:53]
gongyusu [FPGA代码]
+++ pwm_awg [2021/03/08 17:57] (当前版本)
gongyusu
@@ 行 1: / 行 1: @@
 ## DDS+PWM产生任意波形
 ### 工作原理
+  * DDS部分
+  * PWM部分
+  * 模拟链路部分
-### 模拟电路
+### 模拟电路功能介绍
 {{ :fpga_pwm_awg.png |}} <WRAP centeralign> 任意波形发生器模拟电路部分原理图 </WRAP>
 通过调节PWM的占空比（0.5V/3.3V ~ 3V/3.3V）得到等效幅度为0.5V - 3V之间的模拟信号，幅度变化的范围为2.5V，要得到幅度为5Vpp的模拟信号，则放大器的增益设定为G = 2：
@@ 行 20: / 行 23: @@
 如果通过10个点
-{{ :undefined:fpgascope_simulation.jpg |}} <WRAP centeralign> 任意波形发生器模拟电路部分的仿真 </WRAP>
+{{ ::pwm_awg_analog_spred.png |}} <WRAP centeralign> 任意波形发生器模拟电路部分的仿真 - 频率响应（100Hz- 10MHz） </WRAP>
+{{ :pwm_awg_analog_wave.png |}} <WRAP centeralign> 任意波形发生器模拟电路部分的仿真 - 波形（100KHz正弦波） </WRAP>
 ### FPGA代码
 #### DDS得到任意波形
+相位累加器代码：
+<code verilog>
+wire   	[23:0] 	next_phase;
+wire   	[7:0] 	phase;
+reg    	[23:0] 	accumulator;
+assign next_phase = 24'H002222 + accumulator;   // set frequency = 24'H002222 / 2^24 * clock, if PLL not used, clock = 12MHz, output frequency = 6.25KHz
+always @(posedge clk_hs) accumulator <= #1 next_phase;
+assign phase = accumulator[23:16];   	// phase is the high 8 bits as address of the look up table
+wire [9:0] sine_data;                   // sine table is 8 bit wide, 10bit resolution.
+lookup_tables u_lookup_tables(phase, sine_data);
+</code>
+查找表代码：
+<code verilog>
+module lookup_tables(phase, sin_out);
+input  	[7:0] 	phase;    //sine table is 8bits wide, 10 bits resolution
+output 	[9:0] 	sin_out;
+wire     [9:0]   sin_out;
+reg   	[5:0] 	address;
+wire   	[1:0] 	sel;
+wire   	[8:0] 	sine_table_out;
+reg     [9:0]   sine_onecycle_amp;
+//assign sin_out = {1'b0, sine_onecycle_amp[9:1]} + 9'hff;
+assign sin_out = sine_onecycle_amp[9:0];
+	assign sel = phase[7:6];
+   	sin_table u_sin_table(address,sine_table_out);
+always @(sel or sine_table_out or phase)
+begin
+	case(sel)
+'b00: 	begin
+			sine_onecycle_amp = 9'h1ff + sine_table_out[8:0];
+			address = phase[5:0];
+	     	end
+'b01: 	begin
+			sine_onecycle_amp = 9'h1ff + sine_table_out[8:0];
+			address = ~phase[5:0];
+	     	end
+'b10: 	begin
+			sine_onecycle_amp = 9'h1ff - sine_table_out[8:0];
+			address = phase[5:0];
+     		end
+'b11: 	begin
+			sine_onecycle_amp = 9'h1ff - sine_table_out[8:0];
+			address = ~ phase[5:0];
+     		end
+	endcase
+end
+endmodule
+module sin_table(address,sin);
+output [8:0] sin;
+input  [5:0] address;
+reg    [8:0] sin;
+always @(address)
+	begin
+                  case(address)
+'h0: sin=9'h0;
+'h1: sin=9'hC;
+'h2: sin=9'h19;
+'h3: sin=9'h25;
+'h4: sin=9'h32;
+'h5: sin=9'h3E;
+'h6: sin=9'h4B;
+'h7: sin=9'h57;
+'h8: sin=9'h63;
+'h9: sin=9'h70;
+'ha: sin=9'h7C;
+'hb: sin=9'h88;
+'hc: sin=9'h94;
+'hd: sin=9'hA0;
+'he: sin=9'hAC;
+'hf: sin=9'hB8;
+'h10: sin=9'hC3;
+'h11: sin=9'hCF;
+'h12: sin=9'hDA;
+'h13: sin=9'hE6;
+'h14: sin=9'hF1;
+'h15: sin=9'hFC;
+'h16: sin=9'h107;
+'h17: sin=9'h111;
+'h18: sin=9'h11C;
+'h19: sin=9'h126;
+'h1a: sin=9'h130;
+'h1b: sin=9'h13A;
+'h1c: sin=9'h144;
+'h1d: sin=9'h14E;
+'h1e: sin=9'h157;
+'h1f: sin=9'h161;
+'h20: sin=9'h16A;
+'h21: sin=9'h172;
+'h22: sin=9'h17B;
+'h23: sin=9'h183;
+'h24: sin=9'h18B;
+'h25: sin=9'h193;
+'h26: sin=9'h19B;
+'h27: sin=9'h1A2;
+'h28: sin=9'h1A9;
+'h29: sin=9'h1B0;
+'h2a: sin=9'h1B7;
+'h2b: sin=9'h1BD;
+'h2c: sin=9'h1C3;
+'h2d: sin=9'h1C9;
+'h2e: sin=9'h1CE;
+'h2f: sin=9'h1D4;
+'h30: sin=9'h1D9;
+'h31: sin=9'h1DD;
+'h32: sin=9'h1E2;
+'h33: sin=9'h1E6;
+'h34: sin=9'h1E9;
+'h35: sin=9'h1ED;
+'h36: sin=9'h1F0;
+'h37: sin=9'h1F3;
+'h38: sin=9'h1F6;
+'h39: sin=9'h1F8;
+'h3a: sin=9'h1FA;
+'h3b: sin=9'h1FC;
+'h3c: sin=9'h1FD;
+'h3d: sin=9'h1FE;
+'h3e: sin=9'h1FF;
+'h3f: sin=9'h1FF;
+                   endcase
+              end
+endmodule
+</code>
 #### 调用DDS结果通过PWM生成需要的波形
 <code verilog>
+//Generate AWG using 10bit resolution PWM + external RC LPF as DAC, up to 100KHz
+wire [9:0] PWM_WAV_in;
+assign PWM_WAV_in = sine_data[9:0];
+reg [10:0] PWM_WAV_accumulator;
+always @(posedge clk_hs) PWM_WAV_accumulator <= PWM_WAV_accumulator[9:0] + PWM_WAV_in;
+assign pwm_awg = PWM_WAV_accumulator[10];
 </code>