This block includes all power monitoring and control circuitry, internal power supplies, and user power supplies.

As shown in Fig. 23, the Analog Discovery 2's power can be supplied either from the USB port (VBUS) or from an external power supply (J4 connector).

figure_23._usb_power_control

The external power input is protected against reverse voltage; Q4 turns OFF if a floating power supply with negative polarity on central pin of J4 is used. However, the device is not protected for a very unlikely use case:

• Analog Discovery 2 connected to the USB port of a PC which has GND connected to EARTH
• External power supply with negative polarity on central pin of J4 and with exterior pin connected to EARTH.

In this case, the external EARTH loop acts as a shortcut of Q4.

ADCMP671 is a window comparator with the following features:

• Window monitoring with minimum processor I/O
• Individually monitoring N rails with only N + 1 processor I/O
• 400 mV ± 0.275% threshold at VDD = 3.3 V, 25°C
• Supply range: 1.7 V to 5.5 V
• Low quiescent current: 8.55 μA maximum
• Input range includes ground
• Internal hysteresis: 9.2 mV typical
• Low input bias current: ±2.5 nA maximum
• Open-drain outputs
• Power good indication output
• Designated over voltage indication output
• Low profile (1 mm), 6-lead TSOT package

IC48 drives PWRGD output HIGH (turning IC26 ON) when Vext is in the range:

$$4.11V=400mV \cdot \frac {R_{248} + R_{249}+R_{273}}{R_{249} + R_{273}} < V_{ext} < 400mV \cdot \frac {R_{248} + R_{249} + R_{273}}{R_{273}}=5.76V\label{45}\tag{45}$$

The Analog Discovery 2 exhibits two main powering modes: USB and External. Temporary modes (Racing OFF, USB OFF and Racing) are explained here for design clarifications, but have no importance for the user observed behavior.

• Racing OFF – immediately after reset, before FPGA is programmed, if an external power supply is attached and in the right range (PWRGD = HIGH).
• USB OFF – immediately after reset, before FPGA is programmed, if external power supply is missing or out-of-range (PWRGD = LOW).
• USB – all the power is drained from the Vbus (IC21 = ON, IC26 = OFF). The external power supply is either missing or out of the right voltage range. The power available for both User Supplies is limited to 0.7W.

  • Racing – when external power supply is in the right voltage range (PWRGD = HIGH), before WaveForms stops the USB Power Controller. During racing mode, both USB Power Controller (IC21) and External Power controller (IC26) are ON, the device drains power from whatever supply has a higher voltage (D28 and D29 work as a maxim voltage detector). The Racing mode is temporary, it ends when the FPGA is configured and communicates with the WaveForms software. During Racing mode, the power available for User Supplies is limited.
  • External – the device is powered from an external supply (via the 5V DC connector and IC26). Vext is in the range shown by equation \ref{45} (PWRGD = HIGH, and WaveForms already stopped the USB Power Controller (IC21). The User Supplies current and power limits are increased to 700mA or 2.1W each. The only circuit still supplied from the USB VBUS is the USB controller (IC41).

  At Power ON, the FPGA is not programmed, ENVBUS is HiZ, the pulldown resistor R246 turns Q1 OFF, IC21 is ON via R174. The Analog Discovery 2 starts in USB OFF mode (when PWRGD = LOW) or Racing OFF mode (when PWRGD = HIGH). The WaveForms software first configures the FPGA, and the device turns into USB or Racing mode, depending on presence/absence of correct external supply voltage. The FPGA continuously monitors the voltage at the 5V DC connector. When detecting the Racing mode (PWRGD = HIGH), WaveForms sends the command to drive ENVBUS HIGH, turning the USB Power Controller (IC21) OFF, thus switching to External mode.

If external Power Supply is attached after WaveForms started and runs several instruments, the device steps seamlessly trough USB → Racing → External modes. Running instruments are not affected, except User Supplies get more available power.

However, removing the external power supply during External mode is not seamless. Only the USB controller keeps working (as supplied from the USB port). The FPGA gets unpowered and loses configuration data. The device stops all the instruments, EN_VBUS go HiZ, which leads to the USB OFF mode. WaveForms will prompt the user to select the device, which will re-program the FPGA. All the instruments can then be run, in the USB mode.

An ADM1177 Hot Swap Controller and Digital Power Monitor with Soft Start Pin is used to provide USB power compliance during USB and Racing modes (IC21 in Fig. 23).

Remarkable ADM1177 features are:

• Safe live board insertion and removal
• Supply voltages from 3.15 V to 16.5 V
• Precision current sense amplifier
• 12-bit ADC for current and voltage read
• Adjustable analog current limit with circuit breaker
• ±3% accurate hot swap current limit level
• Fast response limits peak fault current
• Automatic retry or latch-off on current fault
• Programmable hot swap timing via TIMER pin
• Soft start pin for reference adjustment and programming of initial current ramp rate
• I2C fast mode-compliant interface (400 kHz maximum)

When enabled, (in USB or Racing modes), IC21 limits the current consumed from the USB port to:

$${I_{limit}} = \frac{{100mV}}{{{R_{173}}}} = \frac{{100mV}}{{0.1\Omega }} = 1A\label{46}\tag{46}$$

For a maximum time of:

$$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{80}=21.7 \left[ ms / \mu F \right] \cdot 0.47\mu F =10.2ms\label{47}\tag{47}$$

If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, IC21 turns off Q2A. A hot swap retry is initiated after:

$$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ \frac{ms}{\mu F} \right] \cdot 0.47 \mu F = 258.5ms\label{48}\tag{48}$$

To avoid high inrush currents at hot swap, Soft Start circuitry limits the current slope to:

$$\frac {dI_{limit}}{dt} = \frac {10 \mu A}{C_{81}} \cdot \frac {1}{10 \cdot R_{173}} =212 \frac {mA}{ms} \label{49}\tag{49}$$

If the current drops below $\;{I_{limit}}$ before ${t_{fault}}$, normal operation begins.

Similarly, IC26 (in Racing or External modes), limits the current consumed from the external power supply to:

$${I_{limit}} = \frac {100mV}{R_{247}} = \frac {100mV}{0.036 \Omega} = 2.78A\label{50}\tag{50}$$

${t_{fault}}$ and ${t_{cool}}$ are same as for IC21, and the current slope limit is:

$$\frac {dI_{limit}}{dt} = \frac{10\mu A}{C_{432}} \cdot \frac{1}{10 \cdot R_{247}}=591 \frac{mA}{ms}\label{51}\tag{51}$$

The Analog Discovery 2 user pins are overvoltage protected. Overvoltage (or ESD) diodes short when a user pin is overdriven by the external circuitry (Circuit Under Test), back powering the input/output block and all the circuits sharing the same internal power supply. If the back-powered energy is higher than the used energy, the bi-directional power supply recovers the difference and delivers it to the previous node in the power chain. Eventually, the back-powering energy could arrive to the USB VBUS, raising the voltage above the 5V nominal value. D28 in Fig. 23 protects the PC USB port against such a situation.

During USB mode, the FPGA constantly reads from IC21 the current value through R173. (Optionally displayed on Main Window/Discovery or Status button). A warning is generated when exceeding 500mA (Status: OC = Over Current). If a value of 600mA is reached and Overcurrent protection is enabled (MainWindow/Device/Settings/Overcurrent protection), WaveForms turns off IC20 (ADP197) shown in Fig. 24 and IC27 shown Fig. 25, disabling the analog blocks and user power supplies.

ADP197 main features:

• Low RDSon of 12mΩ
• Low input voltage range: 1.8V to 5.5V
• 1.2V logic compatible enable logic
• Overtemperature protection
• Ultra-small 1.0mmX1.5mm, 6 ball, 0.5mm pitch WLCSP

figure_24._analog_supplies_control

IC27 in Fig. 25 controls the power available for the user supplies. ADM1270 was selected for its main features:

• Controls supply voltages from 4 V to 60 V
• Gate drive for low voltage drop reverse supply protection
• Gate drive for P-channel FETs
• Inrush current limiting control
• Adjustable current limit
• Foldback current limiting
• Automatic retry or latch-off on current fault
• Programmable current-limit timer for safe operating area (SOA)
• Power-good and fault outputs
• Analog undervoltage (UV) and overvoltage (OV) protection
• 16-lead 3x3mm LFCSP package
• 16-lead QSOP package

figure_25._user_supplies_control

IC27 limits the current consumed by both user power supplies together. The WaveForms software commands the FPGA to change the limit, depending on the power mode.

During USB and Racing modes, SETILIMUSR pin is driven LOW by the FPGA. The voltage at the ISET pin of IC27 is:

$${V_{Iset}} = \frac{{\frac{{{V_{cap}}}}{{{R_{253}}}}}}{{\frac{1}{{{R_{253}}}} + \frac{1}{{{R_{254}}}} + \frac{1}{{{R_{255}}}}}} = \frac{{\frac{{3.6V}}{{10k\Omega }}}}{{\frac{1}{{10k\Omega }} + \frac{1}{{1.74k\Omega }} + \frac{1}{{22.6k\Omega }}}} = 0.5V\label{52}\tag{52}$$

The current limit is set to:

$$I_{limit}= \frac{V_{Iset}}{40 \cdot R_{21}} = \frac{0.5V}{40 \cdot 0.043 \Omega} = 290mA\label{53}\tag{53}$$

During External and OFF modes, SETILIMUSR pin is driven HiZ by the FPGA. The voltage at the ISET pin of IC27 is:

$$V_{Iset}= \frac {V_{cap} \cdot R_{255}}{R_{253} + R_{255}} = \frac{3.6V \cdot 22.6k \Omega }{10k \Omega + 22.6k \Omega} = 2.5V\label{54}\tag{54}$$

The current limit is set to:

$$I_{limit}= \frac {V_{Iset}}{40 \cdot R_{21}} = \frac {2.5V}{40 \cdot 0.043 \Omega} = 1.45A\label{55}\tag{55}$$

In both cases, ${I_{limit}}$ is allowed for a maximum time of:

$$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{170} = 21.7 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 102ms\label{56}\tag{56}$$

If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, IC21 turns off Q2. A hot swap retry is initiated after:

$$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 2.585s\label{57}\tag{57}$$

Soft Start is not used; C183 is a No Load.

If the current drops below ${I_{limit}}$ before ${t_{fault}}$, normal operation begins.

The current limited by equations \ref{53} and \ref{55} is shared by both positive and negative user power supplies. After considering the efficiency of the user supply stages, about 100mA is available for user in both supplies together, in USB Only mode. In External mode, the current/power limit for user is set in the User Voltage Supplies, as explained below.

The user power supplies (Fig. 26) use ADP1612 Switching Converter in Buck-Boost DC-to-DC topology. Main features:

• 1.4A current limit
• Minimum input voltage 1.8V
• Pin-selectable 650 kHz or 1.3 MHz PWM frequency

  • Adjustable output voltage up to 20 V
  • Adjustable soft start
  • Undervoltage lockout

  IC46A/B op amps insert the command voltages $V{SET+_USR}$ and $V{SET-_USR}$, respectively, in the feedback loop. Additionally, IC46B introduces the required inversion for the negative supply.

figure_26._user_power_supplies

Since the op amps are included in negative feedback loops, the input pins voltages are equal:

$${V_{ + IC46A}} = \frac{{\frac{{{V_{OUT + \_USR}}}}{{{R_{188}}}} + \frac{{{V_{SET + \_USR}}}}{{{R_{193}}}}}}{{\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}}}} = {V_{ - IC46A}} = \frac{{\frac{{{V_{FB}}}}{{{R_{266}}}}}}{{\frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}}}\label{58}\tag{58}$$

$${V_{ + IC46B}} = \frac{{\frac{{{V_{OUT - \_USR}}}}{{{R_{187}}}} + \frac{{{V_{FB}}}}{{{R_{270}}}}}}{{\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}}}} = {V_{ - IC46B}} = \frac{{\frac{{{V_{SET - \_USR}}}}{{{R_{190}}}}}}{{\frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}}}\label{59}\tag{59}$$

The input impedances for the op amps are matched:

$$\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}} = \frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}\label{60}\tag{60}$$

$$\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}} = \frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}\label{61}\tag{61}$$

The user voltages are:

$$V_{OUT\;+\_USR}=V_{FB} \cdot \frac{R_{188}}{R_{266}} - V_{SET\;+\_USR} \cdot \frac{R_{188}}{R_{193}}=5.33V-4.87 \cdot V_{SET\;+\_USR}\label{62}\tag{62}$$

$$V_{OUT\;-\_USR}=-V_{FB} \cdot \frac{R_{187}}{R_{270}} + V_{SET\;-\_USR} \cdot \frac{R_{187}}{R_{190}}=-5.33V+4.87 \cdot V_{SET\;-\_USR}\label{63}\tag{63}$$

Where:

$${V_{FB}} = 1.235V\;typical\label{64}\tag{64}$$

IC43 (Fig. 18) generates the setting voltages in the range:

$$0 < V_{SET + \_USR},\; V_{SET - \_USR} < 1.2V\label{65}\tag{65}$$

Which would allow output voltages to be set in the ranges:

$$ - 0.51V \le {V_{SET + \_USR}} < 5.33V\label{66}\tag{66}$$

$$0.51V \ge \; V_{SET - \_USR} > - 5.33V\label{67}\tag{67}$$

The margins allow for compensating the components’ tolerances. After calibration, the WaveForms SW only allows the ranges 0 to +/-5V respectively. Even so, output voltages below absolute value of 0.5V are not guaranteed. With light loads, such voltages might exhibit significant ripple (~15mV).

Each supply can be disabled by the FPGA.

Analog supplies need to have very low ripple to prevent noise from coupling into analog signals. Ferrite beads are used to filter the remaining switching noise and to separate the power supplies that go to the main analog circuit blocks, to avoid crosstalk.

The 3.3V (Fig. 27) and 1.8V Fig. 28 analog power supplies are implemented around an ADP2138 Fixed Output Voltage, 800mA, 3MHz, Step-Down DC-to-DC converter. To insure low output voltage ripple a second LC filter is added and forced PWM mode is selected.

• Input voltage: 2.3 V to 5.5 V
• Peak efficiency: 95%

  • 3 MHz fixed frequency operation
  • Typical quiescent current: 24 μA
  • Very small solution size
  • 6-lead, 1 mm × 1.5 mm WLCSP package
  • Fast load and line transient response
  • 100% duty cycle low dropout mode
  • Internal synchronous rectifier, compensation, and soft start
  • Current overload and thermal shutdown protections
  • Ultra-low shutdown current: 0.2 μA (typical)
  • Forced PWM and automatic PWM/PSM modes

  figure_27._3.3v_internal_analog_power_supply

figure_28._1.8v_internal_analog_power_supply

The -3.3V analog power supply (Fig. 29) is implemented with the ADP2301 Step-Down regulator in an inverting Buck-Boost configuration. See application Note AN-1083: Designing an Inverting Buck Boost Using the ADP2300 and ADP2301. The ADP2301 features:

• 1.2 A maximum load current

  • ±2% output accuracy over temperature range
  • 1.4 MHz switching frequency
  • High efficiency up to 91%
  • Current-mode control architecture
  • Output voltage from 0.8 V to 0.85 × VIN
  • Automatic PFM/PWM mode switching
  • Integrated high-side MOSFET and bootstrap diode,
  • Internal compensation and soft start
  • Undervoltage lockout (UVLO), Overcurrent protection (OCP) and thermal shutdown (TSD)
  • Available in ultrasmall, 6-lead TSOT package

  figure_29._-3.3v_internal_analog_power_supply

The Output voltage is set with an external resistor divider from Vout to FB:

$$\frac{{{R_{180}}}}{{{R_{181}}}} = \;\frac{{ - {V_{out}} - {V_{ref}}}}{{{V_{ref}}}}\label{68}\tag{68}$$

Choosing $R_{181} = 10.2k{\text{\Omega }}$:

$$R_{180}= \frac{3.3V-0.8V}{0.8V} \cdot 10.2k \Omega = 31.87k \Omega \label{69}\tag{69}$$

Closest standard value is $R_{180} = 31.6k{\text{\Omega }}$

The 5.5V and -5.5V supplies Fig. 30 are created with a Sepic-Cuk topology, built around a single ADP1612 Step-Up DC-to DC converter. Both Sepic and Cuk converters are connected to the same switching pin of the regulator. Only the positive Sepic output is regulated, while the negative output tracks the positive one. This is an accepted behavior, since similar load currents are expected on both positive and negative rails.

figure_30._5.5v_internal_analog_supplies

The output current in a Sepic is discontinuous which results in a higher output ripple. To lower this ripple an additional output filter is added to the positive rail.

For more information see application note: AN-1106: An Improved Topology for Creating Split Rails from a Single Input Voltage.

Setting the Output Voltage:

$$\frac{{{R_{184}}}}{{{R_{185}}}} = \;\frac{{{V_{out}} - {V_{ref}}}}{{{V_{ref}}}}\label{70}\tag{70}$$

Choosing ${R_{185}} = 13.7k\Omega$:

$$R_{184}= \frac{5.5V-1.235V}{1.235V} \cdot 13.7k \Omega = 47.31k \Omega\label{71}\tag{71}$$

Closest standard value is ${R_{184}} = 47.5k\Omega$

The 1V digital supply (Fig. 31) is implemented with the ADP2120-1. It has a fixed 1V output voltage option and a ±1.5% output accuracy which makes it suitable for the FPGA internal power supply. It also features:

• 1.25A continuous output current
• 145 mΩ and 70 mΩ integrated MOSFETs

  • Input voltage range from 2.3 V to 5.5 V; output voltage from 0.6 V to VIN
  • 1.2 MHz fixed switching frequency; Selectable PWM or PFM mode operation
  • Current mode architecture
  • Integrated soft start; Internal compensation
  • UVLO, OVP, OCP, and thermal shutdown
  • 10-lead, 3 mm × 3 mm LFCSP_WD package

  figure_31._1v_internal_digital_supply

The 3.3V digital supply (Fig. 32) uses ADP2503-3.3 600mA, 2.5MHz Buck-Boost DC-to-DC Converter:

• Seamless transition between modes

  • 38 μA typical quiescent current
  • 2.5 MHz operation enables 1.5 μH inductor
  • Input voltage: 2.3 V to 5.5 V;
  • Fixed output voltage: 3.3 V
  • Forced fixed frequency
  • Internal compensation
  • Soft start
  • Enable/shutdown logic input
  • Overtemperature protection
  • Short-circuit protection
  • Reverse current capability
  • Undervoltage lockout protection
  • Small 10-lead 3 mm × 3 mm package, 1 mm height profile
  • Compact PCB footprint

  figure_32._3.3v_internal_digital_supply

The main requirement for the 3.3V digital supply is the reverse current capability. When a user pin is overdriven the protection diode opens and back powers circuitry connected to this supply. If the back powered energy is higher than the used energy the regulator delivers it to its input, preventing the 3.3V from rising.

The 1.8V digital power supply (Fig. 33) is implemented with ADP2138-1.8 Fixed Output Voltage, 800mA, 3MHz, Step-Down DC-to-DC converter. This ensures a very small solution size due to the 3MHz switching frequency and the 1mm × 1.5 mm WLCSP package.

The ADP2138 also features:

• Input voltage: 2.3 V to 5.5 V
• Peak efficiency: 95%

  • Typical quiescent current: 24 μA
  • Fast load and line transient response
  • 100% duty cycle low dropout mode
  • Internal synchronous rectifier, compensation, and soft start
  • Current overload and thermal shutdown protections
  • Ultra-low shutdown current: 0.2 μA (typical)
  • Forced PWM and automatic PWM/PSM modes

  figure_33._1.8v_internal_digital_supply

The Analog Discovery 2 uses the AD7415 Digital Output Temperature Sensor (Fig. 34). AD7415 main features are:

• 10-bit temperature-to-digital converter

  • Temperature range: −40°C to +125°C
  • Typical accuracy of ±0.5°C at +40°C
  • SMBus/I2C®-compatible serial interface
  • Temperature conversion time: 29μs (typical)
  • Space-saving 5-lead SOT-23 package
  • Pin-selectable addressing via AS pin

  figure_34._temperature_measurement