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edufpga_20200113 [2020/01/14 20:59] gongyu [Verilog 代码] |
edufpga_20200113 [2020/02/13 17:53] (当前版本) anran [课程平台] |
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| 行 3: | 行 3: | ||
| ### 课程平台 | ### 课程平台 | ||
| - | * [[MAX10M02小脚丫FPGA核心板]] | + | * [[https://www.eetree.cn/wiki/max10m02|MAX10M02小脚丫FPGA核心板]] |
| * [[教师培训用扩展板]] | * [[教师培训用扩展板]] | ||
| * {{:training_board_sch.pdf|培训用扩展板的原理图}} | * {{:training_board_sch.pdf|培训用扩展板的原理图}} | ||
| + | * {{:training_board_sch_v2.pdf|培训用扩展板的原理图V2}} | ||
| * {{:step-max10_原理图.pdf|MAX10M02小脚丫FPGA核心板原理图}} | * {{:step-max10_原理图.pdf|MAX10M02小脚丫FPGA核心板原理图}} | ||
| ### 使用设备 | ### 使用设备 | ||
| - | [[ADALM2000口袋仪器]] | + | * [[https://www.eetree.cn/doc/detail/103|ADALM2000口袋仪器相关资料]] |
| + | * [[https://www.eetree.cn/doc/detail/1132|测试测量仪器参考设计原理图]] | ||
| ### 课程PPT | ### 课程PPT | ||
| 行 21: | 行 23: | ||
| * {{:有限状态机.pptx|有限状态机}} | * {{:有限状态机.pptx|有限状态机}} | ||
| + | --- | ||
| ### Verilog 代码 | ### Verilog 代码 | ||
| - | ==== Counter代码 | + | [[VerilogExamples]] |
| - | ==== PWMPulse代码 | + | |
| + | #### Flash code | ||
| + | <code verilog> | ||
| + | module flash (clk,rst,led); | ||
| + | |||
| + | input clk,rst; | ||
| + | output [7:0] led; | ||
| + | |||
| + | reg [2:0] cnt; | ||
| + | |||
| + | wire clk1h; | ||
| + | |||
| + | counter U1( | ||
| + | .clk(clk), | ||
| + | .rst_n(rst), | ||
| + | .clk_1hz(clk1h) | ||
| + | ); | ||
| + | |||
| + | decode38 U2( | ||
| + | .sw(cnt), | ||
| + | .led(led) | ||
| + | ); | ||
| + | |||
| + | always @(posedge clk or negedge rst) | ||
| + | if(!rst) | ||
| + | cnt <= 1'b0; | ||
| + | else | ||
| + | cnt <= cnt + 1'b1; | ||
| + | |||
| + | endmodule | ||
| + | </code> | ||
| + | |||
| + | #### Counter代码 | ||
| + | <code verilog> | ||
| + | module counter | ||
| + | ( | ||
| + | input clk, | ||
| + | input rst_n, | ||
| + | output reg clk_1hz | ||
| + | ); | ||
| + | |||
| + | parameter NUM = 12_000_000; | ||
| + | |||
| + | reg [23:0] cnt; | ||
| + | always @(posedge clk or negedge rst_n) | ||
| + | if(!rst_n) cnt <= 1'b0; | ||
| + | else if(cnt >= (NUM-1)) cnt <= 1'b0; | ||
| + | else cnt <= cnt + 1'b1; | ||
| + | |||
| + | always @(posedge clk or negedge rst_n) | ||
| + | if(!rst_n) clk_1hz <=1'b0; | ||
| + | else if(cnt <= (NUM>>1)) | ||
| + | clk_1hz <= 1'b0; | ||
| + | else | ||
| + | clk_1hz <= 1'b1; | ||
| + | |||
| + | |||
| + | |||
| + | endmodule | ||
| + | </code> | ||
| + | |||
| + | #### PWMPulse代码 | ||
| <code verilog> | <code verilog> | ||
| //******************************************************** | //******************************************************** | ||
| 行 96: | 行 160: | ||
| </code> | </code> | ||
| - | ==== PWM代码 | + | #### PWM代码 |
| <code verilog> | <code verilog> | ||