Flash code

module flash (clk,rst,led);
 
input clk,rst;
output [7:0] led;
 
reg [2:0] cnt;
 
wire clk1h;
 
counter U1(
		.clk(clk),
		.rst_n(rst),
		.clk_1hz(clk1h)
		);
 
decode38 U2(
		.sw(cnt),
		.led(led)
		);
 
always @(posedge clk or negedge rst)
	if(!rst) 
		cnt <= 1'b0;
	else 
		cnt <= cnt + 1'b1;
 
endmodule

Counter代码

module counter
(
input	clk,
input	rst_n,
output reg	clk_1hz
);
 
parameter NUM = 12_000_000;
 
reg [23:0] cnt;
always @(posedge clk or negedge rst_n)
	if(!rst_n) cnt <= 1'b0;
	else if(cnt >= (NUM-1)) cnt <= 1'b0;
	else cnt <= cnt + 1'b1;
 
always @(posedge clk or negedge rst_n)
	if(!rst_n) clk_1hz <=1'b0;
	else if(cnt <= (NUM>>1)) 
		clk_1hz <= 1'b0;
	else
	   clk_1hz <= 1'b1;
 
 
 
endmodule

PWMPulse代码

//********************************************************
//   Copyright(c)2016, STEP FPGA 
//   All rights reserved
//   File name       :   pwmpulse.v
//   Module name     :   pwmpulse
//   Author          :   STEP
//   Email           :   info@stepfpga.com
//   Data            :   2019/08/01
//   Version         :   V1.0
//   Description     :   
//
//   Modification history
//   ----------------------------------------------------------------------------
// Version       
// Description
//
//********************************************************
 
 
//*******************
//DEFINE MODULE PORT
//*******************
module pwmpulse
(
	//INPUT
	clk			,
	rst		,
	pwmin,
	//OUTPUT
	pwmout			
);
	//*******************
	//DEFINE PARAMETER
	//*******************
	parameter			CYCLE	=	64;//cycle,产生PWM波形周期的计数器值
 
	//*******************
	//DEFINE INPUT
	//*******************
	input 	clk,rst;      			//时钟,复位输入 小脚丫上时钟是12MHz
	input		[7:0] pwmin;				//PWM波形占空比
 
    //*******************
	//DEFINE OUTPUT
	//*******************
	output	reg pwmout;						//PWM输出
 
	//*********************
	//INNER SIGNAL DECLARATION
	//*********************
	reg		[7:0]	count;
 
	//产生波形周期的计数器
	always@(posedge clk)
		if (!rst)
			count<=0;
		else if(count==CYCLE-1)
			count<=0;
		else
			count<=count+1;
 
	//比较后输出PWM值
	always@(*)
		if(pwmin>count[7:0])
			pwmout<=1;
		else
			pwmout<=0;
 
endmodule     

PWM代码

module pwm
(
	//INPUT
	clk			,
	rst		,
 
	pwmout			
);
 
input clk,rst;
output pwmout;
 
wire [7:0] pwmin;
//reg [7:0]pwmin;
 
 
pwmpulse  u1
(
	.clk(clk)		,
	.rst(rst)		,
	.pwmin(pwmin),
	.pwmout(pwmout)			
);
 
 
assign pwmin = 8'd10;
 
endmodule