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async_verilog_source [2020/08/22 16:25]
gongyu 创建 		async_verilog_source [2020/08/22 20:26] (当前版本)
gongyu
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 <code verilog> <code verilog>
 ////////////////////////////////////////////////////////​ ////////////////////////////////////////////////////////​
-// RS-232 ​RX and TX module +// UART RX and TX module 
-// (c) fpga4fun.com & KNJN LLC - 2003 to 2016 +// The UART settings are fixed
- +
-// The RS-232 ​settings are fixed+
 // TX: 8-bit data, 2 stop, no-parity // TX: 8-bit data, 2 stop, no-parity
 // RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course) // RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
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 // TxD_data is latched so that it doesn'​t have to stay valid while it is being sent // TxD_data is latched so that it doesn'​t have to stay valid while it is being sent
  
-parameter ClkFrequency = 25000000; // 25MHz+parameter ClkFrequency = 12000000; // 12MHz
 parameter Baud = 115200; parameter Baud = 115200;
  
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 ); );
  
-parameter ClkFrequency = 25000000; // 25MHz+parameter ClkFrequency = 12000000; // 12MHz
 parameter Baud = 115200; parameter Baud = 115200;
  
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  output tick  // generate a tick at the specified baud rate * oversampling  output tick  // generate a tick at the specified baud rate * oversampling
 ); );
-parameter ClkFrequency = 25000000;+parameter ClkFrequency = 12000000;
 parameter Baud = 115200; parameter Baud = 115200;
 parameter Oversampling = 1; parameter Oversampling = 1;