This chapter shows the features and performances as described in the Analog Discovery 2 Datasheet. Footnotes add detailed information and annotate the HW description in this Manual.
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High Gain: ±2.6V differential input voltage range.
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Low Gain: ±29V differential input voltage range.
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High Gain or Low Gain is used in the analog signal input path for rough scaling. “Digital Zooming” is used for multiple scope scales.
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The Scope bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances (see Figure 21, down). With coax probes and Analog Discovery BNC adapter, the 0.5dB Scope bandwidth is 10 MHz (see Fig. 15).
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As shown in Fig. 12, a ±50V differential input signal does not fit in a single scope screen (ADC range). However, Vertical Position setting allows visualization of either +50V or -50V levels.
8)
Default Scope buffer size is 8kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resource allocation. With no memory allocated to the Digital I/O and reduced memory assigned to the AWG, the scope buffer size can be chosen to be 16kSamples/channel.
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Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.
11)
Real time sampling modes are implemented in the FPGA. The ADC always works at 100MS/s. When a lower sampling rate is required, (108/N samples/sec), N ADC samples are used to build a single recorded sample, either by averaging or decimating. In the Min/Max mode, every 2N samples are used to calculate and store a pair of Min/Max values. The stored sample rate is reduced by half in Min/Max mode.
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In mixed signal mode, the scope and Digital I/O acquisition blocks use the same reference clock, for synchronization.
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This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.
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The AWG DAC always works at 100MS/s. When a lower sampling rate is required, (108/N samples/sec), each sample is sent N times to the DAC.
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The AWG output voltage is limited to ±5V. This refers to the sum of AC signal and DC offset.
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The AWG bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances. With coax probes and Analog Discovery BNC adapter, the 0.5dB AWG bandwidth is 4MHz (see Figure 21).
22)
Default AWG buffer size is 4kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resources allocation. With no memory allocated to the Digital I/O and reduced memory assigned to the Scope, the AWG buffer size can be 16kSamples/channel.
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Real time implemented in the FPGA configuration.
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All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.
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Default Logic Analyzer buffer size is 4kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resource allocation. With no memory allocated to the Scope and AWG, the Logic Analyzer buffer size can be chosen to be 16kSamples/channel.
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Default Pattern Generator buffer size is 1kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resources allocation. With no memory allocated to the Scope and AWG, the Pattern Generator buffer size can be 16kSamples/channel.
39)
WaveForms allows setting the user voltages in the range 0V…5V respectively -0V…-5V. However, voltages below 0.5V, respectively above -0.5V might have excessive ripple and should be used with caution.
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This limit results from the overall device power balance: the power available from the USB port, minus the power internally used by the device, moderated by the user power supplies efficiency. The balance of 500mW is available for both user supplies to share.
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This limit results from the structure of each user power supply (positive and negative). It is not conditioned by the load degree of the complementary user supply.