1 bit adpcm codec
2D FHT
4-bit system
5x4Gbps CRC generator designed with standard cells
8 bit Vedic Multiplier
Adder library
AES128
ANN
Anti-Logarithm (square-root), base-2, single-cycle
BCD adder
Binary to BCD conversions, with LED display driver
Bluespec SystemVerilog Reed Solomon Decoder
Booth Array Multiplier
cavlc decoder
Cellular Automata PRNG
CF Cordic
CF FFT
CF Floating Point Multiplier
Complex Arithmetic Operations
Complex Gaussian Pseudo-random Number Generator
Complex Multiplier
Complex Operations ISE for NIOS II
configurable cordic core in verilog
configurable CRC core
Configurable Parallel Scrambler
CORDIC arctangent for IQ signals

CORDIC core
CRCAHB
cr_div - Cached Reciprocal Divider
DCT - Discrete Cosine Transformer
Discrete Cosine Transform core
double_fpu_verilog
DVB-S2 LDPC Decoder

Elliptic Curve Group
Fixed Point Arithmetic Modules
Fixed Point Math Library for Verilog
Fixed Point Square Root (Recursive Algorithm)
Fixed-point quadratic polynomial
Floating Point Adder and Multiplier
Floating-Point Logarithm Unit
FPGA-based Median Filter
FPU
FPU Double VHDL
FT816Float - Floating point accelerator
Gaussian Noise Generator
Generic Booth Multiplier
Generic Galois LFSR
Generic LFSR Generator
GNExtrapolator
Hardware Division Units
Hardware implementation of Binary Fully Digital Phase Locked Loop
Hardware Load Balancer for Multi-Stage Software Router
HCSA adder and Generic ALU based on HCSA
Heap sorter for FPGA
HIERARCHICAL Integer Multiplier unit
Huffman Decoder
LCD162B Behavior Model
LFSR-Random number generator
Logarithm function, base-2, single-cycle
LZRW1 Compressor Core
Maximum/Minimum binary tree finder
MESI Coherency InterSection Controller
mod3_calc
MODBUS Implementation in VHDL
Model of hybrid classical-quantum computing method
Multiplier library
Multiply-Accumulate Operation (MAC)
Non Linear Pseudo Random Generator
Numbert sort device O(N)
openFPU64
Parameterizable adder tree
Parameterizable integer square root by the digit-by-digit method
Parametrized FFT engine
PID Controler
pipeline mips in vhdl
Population Counter Generator
Priority Encoder
PYRAMID Integer Multiplier unit
QuadFixedPoint32 Arithmetic Unit
radix 4 complex fft
Ray Tracing Arithmetic Engine
Reconfigurable Hardware Platform
Reed-Solomon Decoder
Requantizer
Signed / unsigned multiplier and divider with prime number generator as test circuit
Signed integer divider
SineAndCosineTable
Single 14 Segment Display Driver with Limited ASCII Decoder
Single Clock Unsigned Division Algorithm
Special Functions Units (SFU)
Superscalar Version Of DLX
suslik scalar risc cpu
Tanh Approximation Custom Instruction for NIOS II

Tate Bilinear Pairing
Ternary (3-input) Adder

Tiny Tate Bilinear Pairing
trigonometric functions (degrees) in double fpu
True matrix 3x3 multiplier
Universal multi-function CORDIC
Unsigned serial divider
Versatile counter
Viterbi HDL Code Generator
VIterbi_Tx_Rx
Xilinx Virtex FLoating Point
YAC - Yet Another CORDIC Core
[128bit] Pseudo Random Number Generator Using Linear-feedback Shift Registers