目录

Analog Discovery 2 参考手册

1. 概述

The Digilent Analog Discovery 2™, developed in conjunction with Analog Devices®, is a multi-function instrument that allows users to measure, visualize, generate, record, and control mixed signal circuits of all kinds. The low-cost Analog Discovery 2 is small enough to fit in your pocket, but powerful enough to replace a stack of lab equipment, providing engineering students, hobbyists, and electronics enthusiasts the freedom to work with analog and digital circuits in virtually any environment, in or out of the lab. The analog and digital inputs and outputs can be connected to a circuit using simple wire probes; alternatively, the Analog Discovery BNC Adapter and BNC probes can be used to connect and utilize the inputs and outputs. Driven by the free WaveForms software, the Analog Discovery 2 can be configured to work as any one of several traditional instruments, which include:

图1. Analog Discovery 2的图片

The Analog Discovery 2 was designed for students in typical university-based circuits and electronics classes. Its features and specifications, as well as the additional requirements of operating from USB or external power, maintaining the small and portable form factor, the robustness to withstand student use in a variety of environments, and low-cost are based directly on feedback that was obtained from numerous professors from several universities. Meeting all of these requirements proved challenging; however, the task ultimately generated some new and innovative circuits. This document describes the Analog Discovery 2's circuits, with the intent of providing a better understanding of its electrical functions, operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information to enable complete duplication of the Analog Discovery 2, or to allow users to design custom configurations for programmable parts in the design.

连线图

Analog Discovery 2 Pinout.

1.1 架构及结构框图

Analog Discovery 2's high-level block diagram is presented in Fig. 2 below. The core of the Analog Discovery 2 is the Xilinx® Spartan®-6 FPGA (specifically, the XC6SLX16-1L device). The WaveForms application automatically programs the Discovery’s FPGA at start-up with a configuration file designed to implement a multi-function test and measurement instrument. Once programmed, the FPGA inside the Discovery communicates with the PC-based WaveForms application via a USB 2.0 connection. The WaveForms software works with the FPGA to control all the functional blocks of the Analog Discovery 2, including setting parameters, acquiring data, and transferring and storing data.

Signals in the Analog Input block, also called the Scope, use “SC” indexes to indicate they are related to the scope block. Signals in the Analog Output block, also called AWG, use “AWG” indexes, and signals in the Digital block use a D index – all of the instruments offered by the Discovery 2 and WaveForms use the circuits in these three blocks. Signal and equations also use certain naming conventions. Analog voltages are prefixed with a “V” (for voltage), and suffixes and indexes are used in various ways: to specify the location in the signal path (IN, MUX, BUF, ADC, etc.); to indicate the related instrument (SC, AWG, etc.); to indicate the channel (1 or 2); and to indicate the type of signal (P, N, or diff). Referring to the block diagram in Fig. 2 below:

In the sections that follow, schematics are not shown separately for identical blocks. For example, the Scope Input Divider and Gain Selection schematic is only shown for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As examples, in equation \ref{4} below, $V_{in diff}$ does not contain the instrument index (which by context is understood to be the Scope), nor the channel index (because the equation applies to both channels 1 and 2). In equation \ref{3}, the type index is also missing because $V_{mux}$ and $V_{in}$ refer to any of P (positive), N (negative) or diff (differential) values.

Figure 2. Analog Discovery 2 block diagram.

图2 Analog Discovery 2框图

2. 示波器

Important Note: Unlike traditional inexpensive scopes, the Analog Discovery 2 inputs are fully differential. However, a GND connection to the circuit under test is needed to provide a stable common mode voltage. The Analog Discovery 2 GND reference is connected to the USB GND. Depending on the PC powering scheme, and other PC connections (Ethernet, audio, etc. – which might also be grounded) the Analog Discovery 2 GND reference might be connected to the whole GND system and ultimately to the power network protection (earth ground). The circuit under test might also be connected to earth or possibly floating. For safety reasons, it is the user’s responsibility to understand the powering and grounding scheme and make sure that there is a common GND reference between the Analog Discovery 2 and the circuit under test, and that the common mode and differential voltages do not exceed the limits shown in equation \ref{1}. Furthermore, for distortion-free measurements, the common mode and differential voltages need to fit into the linear range shown in Figs. 12 and 13. For those applications which scope GND cannot be the USB ground, a USB isolation solution, such as what is described in ADI’s CN-0160 can be used; however, this will limit things to USB full speed (12 Mbps), and will impact the update rate (screen refresh rates, not sample rates) of the Analog Discovery 2.

2.1. 示波器输入分压及增益选择

Figure 3 shows the scope input divider and gain selection stage.

两个对称的R-C分压电路提供了:

受限于C1到C24，示波器输入的最大电压范围为: $$-50V<V_{inP},V_{inN}<50V\label{1}\tag{1}$$

为避免信号失真讲ADG612的ESD二极管开路导致的输入信号的最大摆动幅度：(对于低增益和高增益都适用):

$$-26V<V_{inP},V_{inN}<26V\label{2}\tag{2}$$

模拟开关(ADG612)允许通过FPGA的信号(ENHGSC1, ENLGSC1)来选择高增益或者低增益。差分路径的P和N支路都一起切换。

采用具有4路开关的ADG612主要是因为它能够提供优秀的阻抗和带宽参数:

低增益为: $$\frac {V_{mux}}{V_{in}}=\frac {R_6}{R_1+R_4+R_6}=0.019\label{3}\tag{3}$$

低增益用于输入电压为：$$| V_{indiff} | = | V_{inP}-V_{inN} |<50V\label{4}\tag{4}$$

高增益为：$$\frac {V_{mux}}{V_{in}} = \frac {R_4 + R_6}{R_1 + R_4 + R_6} = 0.212 \label{5}\tag{5}$$

高增益用于输入电压为: $$|V_{indiff}| = |V_{inP} - V_{inN}|<7V \label{6}\tag{6}$$

Figure 3. 输入分压合增益选择

图3.输入分压合增益选择

2.2. 示波器缓冲

一级同相运放提供了非常高的阻抗作为输入分压电路的负载 (Fig. 4).

Figure 4. Scope buffer.

图4 示波器缓冲

AD8066有用的特性有:

图中的电阻和电容帮助最大化带宽并减低峰值(在跟随的状态时可能非常剧烈).

The AD8066 is supplied ± 5.5V.

最大输入电压摆动: $-5.5V<V_{mux P},V_{mux N}<2.2V\label{7}\tag{7}$

最大输出电压摆动: $-5.38V<V_{buf P},V_{buf N}<5.4V\label{8}\tag{8}$

增益为: $$\frac {V_{buf}}{V_{mux}}=1\label{9}\tag{9}$$

2.3. 示波器参考和偏置

Figure 5 shows the scope voltage reference sources and offset control stage. A low noise reference is used to generate reference voltages for all the scope stages. Buffered and scaled replicas of the reference voltages are provided for the buffer stages and individually for each scope channel to minimize crosstalk. A dual channel DAC generates the offset voltages, to be added over the input signal, for vertical position. Buffers are used to provide low impedance.

ADR3412ARJZ – Micropower, high accuracy voltage reference:

AD5643 - Dual 14-Bit nanoDAC®:

ADA4051-2 – Micropower, Zero-drift, Rail-to-rail input/output Op Amp:

The reference voltages generated for the scope stages are: $$V_{refSC}=V_{ref1V2}\cdot \left( 1+ \frac {R_{79}}{R_{80}} \right) =2V \label{10}\tag{10}$$

The offset voltages for the scope stages are: $$0 \le V_{offSC} = V_{outAD5643} \cdot \left( 1+ \frac {R_{77}}{R_{78}} \right) < 4.044V \label{11}\tag{11}$$

Figure 5. Scope reference and offset. figure_5._scope_reference_and_offset

2.4. Scope Driver

ADA4940 ADC driver features:

IC2 (Fig. 6) is used for:

Figure 6. Scope driver

figure_6._scope_driver

ADA4940 is supplied ±3.3V. The common mode voltage range is:

$$-3.5V<V_{+ADA4940} = V_{-ADA4940} < 2.1V \label{12}\tag{12}$$

The signal gain is:

$$\frac{V_{ADCdiff}}{V_{bufdiff}}=\frac{R_9}{R_8}=\frac{R_{17}}{R_{16}}=1.77\label{13}\tag{13}$$

The offset gain is:

$$\frac {V_{ADCdiff}}{V_{offSC} - V_{refSC}} = \frac {R_9}{R_3} = \frac {R_{17}}{R_{22}} = 1 \label{14}\tag{14}$$

The common mode gain is:

$$\dfrac{V_{CM}}{V_{ADCP}+V_{ADCN}/2}=1\label{15}\tag{15}$$

The clamping voltages are:

$$V_{Out-IC2A}=V_{CM}-\frac{AVCC1V8}{2}\cdot\frac{R_{23}}{R_{25}} = 0.9V-\frac{1.8V}{2}\cdot\frac{4.99K}{6.34K}=0.2V\label{16}\tag{16}$$

$$V_{Out+IC2A}=V_{CM}-\frac{AVCC1V8}{2}\cdot\frac{R_{23}}{R_{25}} = 0.9V+\frac{1.8V}{2}\cdot\frac{4.99K}{6.34K}=1.6V\label{17}\tag{17}$$

D1, D2 clamp the VADC signals to the protected levels of:

$$-0.1V<V_{+ADA4940}=V_{-ADA4940}<1.9V\label{18}\tag{18}$$

2.5. Clock Generator

A precision oscillator (IC31) generates a low jitter, 20 MHz clock (see Fig. 8).

The ADF4360-9 Clock Generator PLL with Integrated VCO is configured for generating a 200 MHz differential clock for the ADC and a 100 MHz single-ended clock for the DAC.

Analog Devices ADIsimPLL software was used for designing the clock generator (see Fig. 7). The PLL filter is optimized for constant frequency (low Loop Bandwidth = 50 kHz and Phase Margin = 60°). Simulation results are shown below. The Phase jitter using a brick wall filter (10.0 kHz to 100 kHz) is 0.04° rms.

Figure 7. Phase noise figure for the clock generator. figure_7._phase_noise_figure_for_the_clock_generator

Figure 8. Clock generator. figure_8._clock_generator

2.6. Scope ADC

2.6.1. 模拟部分

Analog Discovery 2 采用了双通道、高速、14位、105Msps ADC（型号为AD9648), 如图图9 .

图9. ADC-模拟部分. figure_9._adc_-_analog_section

AD9648的主要性能:

The differential inputs are driven via a low-pass filter comprised of C141 together with R10 through R13, in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by two for operating at a constant 100 MHz sampling rate. An external reference voltage is used, buffered by IC 19. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage.

差分输入电压范围:

$$-1V<V_{ADC\;diff}<1V\label{19}\tag{19}$$

2.6.2. Digital Section

The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8V.

To minimize the number of used FPGA pins; a multiplexed mode is used, to combine the two channels on a single data bus. CLKOUTSC is provided to the FPGA for synchronizing data (see Fig. 10). Figure 10. ADC - digital section. figure_10._adc_-_digital_section —- ===== 2.7. Scope Signal Scaling ===== Combining Gain equations \ref{3}, \ref{5}, \ref{9}, \ref{13}, \ref{14}, and \ref{15} from previous chapters, the total scope gains are: $$Low \; gain = \frac{V{ADC\;diff}}{V{in\;diff}}=0.034$$ $$High \; gain = \frac{V{ADC\;diff}}{V_{in\;diff}}=0.375\label{20}\tag{20}$$ Combining the ADC input voltage range shown in \ref{19} with $V_{offSC}$ at the midrange of \ref{11} (scope vertical position at 0), the Vin range is:

$$at \; low \; gain: -30V<V_{in\;diff}<28.6V$$ $$at \; high \; gain: -2.7V<V_{in\;diff}<2.6V\label{21}\tag{21}$$

To cover component value tolerances and to allow software calibration, only the ranges below are specified.

$$at \; low \; gain: -25V<V_{in\;diff}<25V$$ $$at \; high \; gain: -2.5V<V_{in\;diff}<2.5V\label{22}\tag{22}$$

With the 14-bit ADC, the absolute resolution of the scope is:

$$at \; low \; gain: \frac{58.6V}{2^{14}}=3.58mV$$ $$at \; high \; gain: \frac{5.3V}{2^{14}}=0.32mV\label{23}\tag{23}$$

The effect of the offset setting (scope vertical position) can be calculated from \ref{10}, \ref{11} and \ref{14}:

$$-2V<V_{offSC}-V_{refSC}<2.044V\label{24}\tag{24}$$

The vertical position setting moves the signals vertically on the scope screen (relative to vertical screen center) by $V_{off eq in}$:

$$at \; low \; gain: -59.3V<V_{off\;eq\;in}<59.3V$$ $$at \; high \; gain: -5.39V<V_{off\;eq\;in}<5.39V\label{25}\tag{25}$$

The above adds an equivalent offset voltage $V_{off eq in}$ to $V_{in diff}$, translating the ranges in \ref{21} and \ref{22} by $V_{off eq in}$ , up to the limits in \ref{25}.

Equations \ref{2}, \ref{7}, \ref{8}, \ref{12}, and \ref{19} show signal range boundaries for keeping ICs in the input/output voltage ranges. Combining these with the gain equations, the overall linear scope operation range is shown Figs. 11 & 12. Each equation is represented by a closed polygon. Each figure is shown at the full range and at a detailed range. Separate figures are shown for low-gain and for high-gain. The right hand diagrams use $V_{in diff}$ and $V_{in CM}$ coordinates while left hand ones use $V_{inP}$ and $V_{inN}$ coordinates.

To be visible on the scope screen and not distorted, a signal should be included in all the solid line polygons of a figure (linear range = geometrical intersection of the surfaces).

Only the differential input voltage is shown on the scope screen. The common mode voltage information is removed by the differential structure of the Analog Discovery 2 scope. A signal overpassing the linear range will be distorted on the scope screen, i.e. the graphical representation will be clamped. In the diagrams below, a signal outside the linear range will be clamped to the closest point in the linear range. The clamping point is not necessarily at the scope screen top or bottom edge, as explained below.

Figure 11. Scope input signal range. Scale: Low gain, in terms of: VinP and VinN (left), VinDiff and VinCM (right). Size: Full range (up), detail (down). figure_11._scope_input_signal_range._scale_-_low_gain_in_terms_of_-_vinp_and_vinn_left_vindiff_and_vincm_right_._size_-_full_range_up_detail_down

The dashed rectangles represent the display area on the scope screen. There are three dashed rectangles in each diagram: the middle one corresponds to the vertical position set to 0 (VoffSc = 2.022V in equation \ref{11}. The left one shows the display area when vertical position is set to maximum (VoffSc = 4.044V), and the right one corresponds to the minimum (negative) vertical position (VoffSc = 0V). Any intermediate vertical position is possible, moving the displayable area (virtual dashed rectangle) to any intermediate position. A signal crossing the long side of the dashed rectangle exceeds the displayable input voltage range causing the ADC to saturate (either at zero or at Full Scale). This is represented on the scope screen with dashed line warning to the user.

Figure 12. Scope input signal range. Scale - High gain, in terms of - VinP and VinN (left), VinDiff and VinCM (right). Size - Full range (up), detail (down). figure_12._scope_input_signal_range._scale_-_high_gain_in_terms_of_-_vinp_and_vinn_left_vindiff_and_vincm_right_._size_-_full_range_up_detail_down

A signal keeping within the dashed rectangle but crossing any solid line overrides electrical limits of intermediate circuits in the signal path (see the legend of the figures). This results in distorting the signal without saturating the ADC. The software has no information about this situation and cannot warn the user with specific signal representation. It is the user’s responsibility to understand and avoid such situations.

For low gain (Fig. 11), the simple condition to stay in the linear range is to keep both positive and negative inputs $V_{inP}$, $V_{inN}$ in the ±26V range (as shown by equation \ref{2}).

For high gain (Fig. 12), by combining equations \ref{7} and \ref{5}, both positive and negative inputs in must stay in the range:

$$-26V<V_{inP},V_{inN}<10V\label{26}\tag{26}$$

Additionally, the differential input signal (combined with the equivalent offset voltage – vertical position) is visible only within the range:

$$-7.5V<V_{inDiff}<7.5V\label{27}\tag{27}$$

Note the difference between typical parameter values considered by the figures and the safer min/max values used for the equations.

Figure 13 shows an example of a signal distorted due to a common mode input voltage that is too large. The grey line is the reference, not distorted, signal. The differential input voltage is a 4Vpp triangle on top of a -5V DC component. The common mode input voltage is 10V. The vertical position of the scope is set to 5V and high gain is selected. The yellow line shows an identical signal, except the common mode input voltage is 15V.

Figure 13. Common mode input voltage limitation. figure_13._common_mode_input_voltage_limitation

2.8 Scope Spectral Characteristics

Figure 14 shows a typical spectral characteristic of the scope. An Agilent 3320A 20 MHz Function/Arbitrary Waveform Generator was used to generate the input signal of 1VRMS. The signal swept from 100 Hz to 30 MHz. A coax cable and a Digilent Discovery BNC adapter were used to connect the input signal to the Discovery inputs.

The Network Analyzer was used, the WaveGen was set to External, the Gain was set at x10 (high-gain) for the upper figure, and x0.1 (low-gain) for the lower one. For both scales, the 3dB bandwidth is 30 MHz+. The 0.5dB bandwidth is 10 MHz and the 0.1dB bandwidth is 5 MHz. The standard -3dB bandwidth definition is derived from filter theory. At cutout frequency, the scope attenuates the spectral components by 0.707, assuming an error of ~30%, way too high for a measuring instrument. The bandwidth with a specified flatness is useful to better define the scope spectral performances. The Analog Discovery 2 exhibits 10 MHz @ 0.5dB, meaning that a 10 MHz sinusoidal signal is shown with a flatness error of a max 5.6%. 5 MHz @ 1dB means that a 5 MHz sinusoidal signal is shown with a flatness error of a max 1.5%.

Figure 14. Scope spectral characteristic diagram. Low gain (up), high gain (down). figure_14._scope_spectral_characteristic_diagram._low_gain_up_high_gain_down

As shown above, the measurements in Fig. 14 were taken with a coax cable and a Digilent Discovery BNC adapter. This is the optimal setup that allows maximal Analog Discovery spectral performance. The wire kit included with the Analog Discovery 2 is a cheap, easy-to-use probing solution. However, the wire kit reduces the bandwidth of the scope and is susceptible to inducing noise and crosstalk from adjacent circuits. Fig. 21 shows the spectral characteristic diagram for the AWG connected to the scope with the wire kit.

3. Arbitrary Waveform Generator

3.1. AWG DAC

The Analog Devices AD9717 dual, low-power 14-bit TxDAC digital-to-analog converter is used to generate the wave (Fig. 15). The main features are:

The parallel Data Bus and the SPI configuration bus are driven by the FPGA. The single ended 100 MHz clock is provided by the clock generator. External Vref1VAWG reference voltage is used. The output currents (IoutAWGxP and _N) are converted to voltages in the I/V stage. The Full Scale is set via the FSADJx pins (see Fig. 16). The ADG787 2.5Ω CMOS Low Power Dual 2:1 MUX/DEMUX is used to connect $text_r{set}}$ of either 8kΩ (for high gain) or 32kΩ (for low gain) from FSADJx pin to GND.

Figure 15. DAC. figure_15._dac

The ADG787 features:

Figure 16. DAC - Gain set. figure_16._dac_-_gain_set

3.2. AWG Reference and Offset

As shown in Fig. 17, the reference voltage for the AWG is generated by IC42 (ADR3412ARJZ). A divided version is provided to the DAC:

$$V_{ref1V\_AWG}=V_{ref1V2\_AWG} \cdot \frac{R_{41}}{R_{39}+{R_{41}}}=1V\label{28}\tag{28}$$

Figure 17. DAC - Reference voltages. figure_17._dac_-_reference_voltages

Buffered versions are provided to the I/V stages and individually for each AWG channel to minimize crosstalk.

The Full Scale DAC output current is:

$$I_{outAWGFS}=32 \cdot \frac{V_{ref1V\_AWG}}{R_{set}}\label{29}\tag{29}$$

For high-gain:

$$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{8k \Omega}=4mA\label{30}\tag{30}$$

For low-gain:

$$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{32k \Omega}=1mA\label{31}\tag{31}$$

An AD5645R Quad 14-bit nanoDAC generates the offset voltages to add a DC component to the AWG output signal (Fig. 18). The same circuit also generates VSET+ USR and VSET- USR, used to set the +/- user supply voltages.

The Full Scale voltage of all IC43 outputs is:

$$V_{offAWGFS}=V_{SET\_USRFS}=V_{ref1V2AWG}=1.2V\label{32}\tag{32}$$

3.3. AWG I/V

IC 15 in Fig. 19 converts the DAC output currents to a bipolar voltage.

Important AD8058 features:

$$V_{Audio}=I_{outAWGP} \cdot R_{148}-I_{outAWGN} \cdot R_{142}=$$ $$=( 1-2 \cdot \{ A_U \} ) \cdot I_{outAWGFS} \cdot R_{142}=\{ A_b \} \cdot I_{outAWGFS} \cdot R_{142}\label{33}\tag{33}$$

Where:

$$\left\{ {{A_U}} \right\} = \frac{D}{{{2^N}}} \in \left[ {\left. {0 \ldots 1} \right)} \right.;\; - \;normalized\;unipolar\;DAC\;input\;number$$

$$\left\{ {{A_B}} \right\} = \left( {1 - 2 \cdot \left\{ {{A_U}} \right\}} \right) \in \left[ {\left. { - 1 \ldots 1} \right)} \right.;\; - \;normalized\;bipolar\;DAC\;input\;number\;\left( {binary\;offset} \right)$$

$$D \in \left[ {\left. {0 \ldots {2^{14}}} \right)} \right. = \left[ {0 \ldots {2^{14}} - 1} \right];\; - \;integer\;unipolar\;DAC\;input\;number\label{34}\tag{34}$$

The Voltage range extends between:

$$ - V_{AudioFS} \le V_{Audio} < - V_{AudioFS}\label{35}\tag{35}$$

Where (for high gain, respectively, low gain):

$$V_{AudioFS\;HG}=I_{outAWGFS\;HG} \cdot R_{142}=496mV$$ $$V_{AudioFS\;LG}=I_{outAWGFS\;LG} \cdot R_{142}=124mV\label{36}\tag{36}$$

Figure 19. AWG I/V and out.

//{{anchor:figure_19:Figure 19. AWG I/V and out.}}//

3.4. AWG Out

IC16 in Fig. 19 is the output stage of the AWG. AD8067 features:

$$\frac{1}{{{{\mathbf{R}}_{140}}}} + \frac{1}{{{{\mathbf{R}}_{141}}}} + \frac{1}{{{{\mathbf{R}}_{144}}}} = \frac{1}{{{{\mathbf{R}}_{147}}}} + \frac{1}{{{{\mathbf{R}}_{149}}}}\label{37}\tag{37}$$

$$V_{outAWG}=-V_{Audio} \cdot \frac{R_{141}}{R_{144}}+\left(2 \cdot V_{offAWG}-V_{ref1V2AWG}\right) \cdot \frac{R_{141}}{R_{140}}\label{38}\tag{38}$$

The first term in equation \ref{38} represents the actual wave amplitude, with a range of:

$$ - 5.45V < - 5V < V_{ACoutAWG\;HG} < 5V < 5.45V$$ $$ - 1.36V < 1.25V < V_{ACoutAWG\;LG} < 1.25V < 1.36V\label{39}\tag{39}$$

Low-gain is used to generate low amplitude signals with improved accuracy. Any amplitude of the output signal is derivable by combining LowGain/HighGain setting (rough) with the digital signal amplitude (fine).

With the 14-bit DAC, the absolute resolution of the AWG AC component is:

$$at\;Low\;Gain:\;\;\;\frac{{2.72V}}{{{2^{14}}}} = 166\mu V$$ $$at\;High\;Gain:\;\;\;\;\;\frac{{10.9V}}{{{2^{14}}}} = 665\mu V\label{40}\tag{40}$$

The second term in equation \ref{38} shows the DC component (AWG offset), with a range of (for either LowGain or HighGain):

$$ - 5.5V < 5V < V_{DCoutAWG} < 5V < 5.5V\label{41}\tag{41}$$

AD8067 is supplied with $\pm 5.5V$; to avoid saturation the user should keep the sum of AC and DC components in \ref{38} to:

$$ - 5.5V < 5V < V_{outAWG} < 5V < 5.5V\label{42}\tag{42}$$

Only bolded ranges are used in equations \ref{39}, \ref{41}, and \ref{42}, for providing tolerance margins.

The R145 PTC thermistor provides thermal protection in case of an output shortcut.

3.5. Audio

A stereo audio output combines the two AWG channels (Fig. 20). AD8592 was used for its features:

$$V_{outIC18}=-2 \cdot V_{Audio}+1.5V\label{43}\tag{43}$$

The first term in equation \ref{43} is the audio signal. The second term is the common mode DC component, removed by AC coupling.
The audio signal range is:

$$V_{AudioJack}=-2 \cdot V_{Audio}$$ $$-992mV < V_{AudioJack} < 992mV \left( High\;Gain \right)$$ $$-248mV < V_{AudioJack} < 248mV \left( Low\;Gain \right)\label{44}\tag{44}$$

Figure 20. Audio. figure_20._audio

3.6. AWG Spectral Characteristics

Figure 21 shows the typical spectral characteristic of the AWG. In the first experiment (up), a coax cable and a Digilent Discovery BNC adapter were used to connect the AWG signal to the Scope inputs. For the second experiment (down), the AWG was connected to the scope inputs via the Analog Discovery wire kit. The Analog Discovery 2 Scope hardware was considered a reference for the experiments above because it has preferred spectral characteristics to the AWG.
The Network Analyzer virtual instrument in WaveForms is used to perform synchronized signal synthesis and acquisition. It takes control of channel 1 of AWG and of both scope channels. Start/Stop frequencies are set to 100 Hz/25 MHz, respectively. Sinus amplitude is set to 1V. The characteristic is built in 100 steps. The 3dB bandwidth is 12 MHz with the coax cable and 9 MHz with the wire kit. The 0.5dB bandwidth is 4 MHz with the coax cable and 2.9 MHz with the wire kit. The 0.1dB is 1 MHz with the coax cable and 800 kHz with the wire kit.

Figure 21. AWG spectral characteristics. With Analog Discovery BNC Adapter and BNC cable from AWG to Scope (up). With the wire kit (down). figure_21._awg_spectral_characteristics._with_analog_discovery_bnc_adapter_and_bnc_cable_from_awg_to_scope_up_._with_the_wire_kit_down

4. Calibration Memory

The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, capacitance, offsets, bias currents, etc.) as typical values and tolerances. The equations in previous chapters consider typical values. Component tolerances affect DC, AC, and CMMR performances of the Analog Discovery 2. To minimize these effects, the design uses:

A software calibration is performed on each device as a part of the manufacturing test. AWG signals are passed to a reference instrument and reference signals are connected to the Scope inputs. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Analog Discovery 2 device, as Factory Calibration. The WaveForms software allows the user performing an in-house calibration and overwrite the Calibration Data. Returning to Factory Calibration is always possible.

The WaveForms Software reads the calibration parameters from the connected Analog Discovery 2 and uses them to correct both generated and acquired signals.

5. Digital I/O

Figure 22 shows half of the Digital I/O pin circuitry (the other half is symmetrical). J3 is the Analog Discovery 2 user signal connector.

General purpose FPGA I/O pins are used for Analog Discovery 2 Digital I/O. FPGA pins are set to SLOW slew rate and 4mA drive strength, with no internal pull.

PTC thermistors provide thermal protection in case of shortcuts. Schottky Diodes double the internal FPGA ESD protection diodes for increasing the acceptable current in case of overvoltage. Nominal resistance of the PTCs (220Ω) and parasitical capacitance of the Schottky diodes (2.2pF) and FPGA pins (10pF) limit the bandwidth of the input pins. For output pins, the PTCs and the load impedance limit the bandwidth and power.

Input and output pins are LVCMOS3V3. Inputs are 5V tolerant. Overvoltage up to ±20V is supported.

Figure 22. Digital I/O. figure_22._digital_i_o

6. 电源和控制

此部分为所有的电源监测和控制电路，内部的电源以及用户电源。

6.1. USB Power Control

As shown in Fig. 23, the Analog Discovery 2's power can be supplied either from the USB port (VBUS) or from an external power supply (J4 connector).

Figure 23. USB power control. figure_23._usb_power_control

The external power input is protected against reverse voltage; Q4 turns OFF if a floating power supply with negative polarity on central pin of J4 is used. However, the device is not protected for a very unlikely use case:

In this case, the external EARTH loop acts as a shortcut of Q4.

ADCMP671 is a window comparator with the following features:

IC48 drives PWRGD output HIGH (turning IC26 ON) when Vext is in the range:

$$4.11V=400mV \cdot \frac {R_{248} + R_{249}+R_{273}}{R_{249} + R_{273}} < V_{ext} < 400mV \cdot \frac {R_{248} + R_{249} + R_{273}}{R_{273}}=5.76V\label{45}\tag{45}$$

The Analog Discovery 2 exhibits two main powering modes: USB and External. Temporary modes (Racing OFF, USB OFF and Racing) are explained here for design clarifications, but have no importance for the user observed behavior.

If external Power Supply is attached after WaveForms started and runs several instruments, the device steps seamlessly trough USB → Racing → External modes. Running instruments are not affected, except User Supplies get more available power.

However, removing the external power supply during External mode is not seamless. Only the USB controller keeps working (as supplied from the USB port). The FPGA gets unpowered and loses configuration data. The device stops all the instruments, EN_VBUS go HiZ, which leads to the USB OFF mode. WaveForms will prompt the user to select the device, which will re-program the FPGA. All the instruments can then be run, in the USB mode.

An ADM1177 Hot Swap Controller and Digital Power Monitor with Soft Start Pin is used to provide USB power compliance during USB and Racing modes (IC21 in Fig. 23).

Remarkable ADM1177 features are:

When enabled, (in USB or Racing modes), IC21 limits the current consumed from the USB port to:

$${I_{limit}} = \frac{{100mV}}{{{R_{173}}}} = \frac{{100mV}}{{0.1\Omega }} = 1A\label{46}\tag{46}$$

For a maximum time of:

$$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{80}=21.7 \left[ ms / \mu F \right] \cdot 0.47\mu F =10.2ms\label{47}\tag{47}$$

If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, IC21 turns off Q2A. A hot swap retry is initiated after:

$$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ \frac{ms}{\mu F} \right] \cdot 0.47 \mu F = 258.5ms\label{48}\tag{48}$$

To avoid high inrush currents at hot swap, Soft Start circuitry limits the current slope to:

$$\frac {dI_{limit}}{dt} = \frac {10 \mu A}{C_{81}} \cdot \frac {1}{10 \cdot R_{173}} =212 \frac {mA}{ms} \label{49}\tag{49}$$

If the current drops below $\;{I_{limit}}$ before ${t_{fault}}$, normal operation begins.

Similarly, IC26 (in Racing or External modes), limits the current consumed from the external power supply to:

$${I_{limit}} = \frac {100mV}{R_{247}} = \frac {100mV}{0.036 \Omega} = 2.78A\label{50}\tag{50}$$

${t_{fault}}$ and ${t_{cool}}$ are same as for IC21, and the current slope limit is:

$$\frac {dI_{limit}}{dt} = \frac{10\mu A}{C_{432}} \cdot \frac{1}{10 \cdot R_{247}}=591 \frac{mA}{ms}\label{51}\tag{51}$$

The Analog Discovery 2 user pins are overvoltage protected. Overvoltage (or ESD) diodes short when a user pin is overdriven by the external circuitry (Circuit Under Test), back powering the input/output block and all the circuits sharing the same internal power supply. If the back-powered energy is higher than the used energy, the bi-directional power supply recovers the difference and delivers it to the previous node in the power chain. Eventually, the back-powering energy could arrive to the USB VBUS, raising the voltage above the 5V nominal value. D28 in Fig. 23 protects the PC USB port against such a situation.

6.2. Analog Supplies Control

During USB mode, the FPGA constantly reads from IC21 the current value through R173. (Optionally displayed on Main Window/Discovery or Status button). A warning is generated when exceeding 500mA (Status: OC = Over Current). If a value of 600mA is reached and Overcurrent protection is enabled (MainWindow/Device/Settings/Overcurrent protection), WaveForms turns off IC20 (ADP197) shown in Fig. 24 and IC27 shown Fig. 25, disabling the analog blocks and user power supplies.

ADP197 main features:

Figure 24. Analog Supplies control.

//{{anchor:figure_24:Figure 24. Analog Supplies control.}}//

6.3. User Supplies Control

IC27 in Fig. 25 controls the power available for the user supplies. ADM1270 was selected for its main features:

Figure 25. User supplies control. figure_25._user_supplies_control

IC27 limits the current consumed by both user power supplies together. The WaveForms software commands the FPGA to change the limit, depending on the power mode.

During USB and Racing modes, SETILIMUSR pin is driven LOW by the FPGA. The voltage at the ISET pin of IC27 is:

$${V_{Iset}} = \frac{{\frac{{{V_{cap}}}}{{{R_{253}}}}}}{{\frac{1}{{{R_{253}}}} + \frac{1}{{{R_{254}}}} + \frac{1}{{{R_{255}}}}}} = \frac{{\frac{{3.6V}}{{10k\Omega }}}}{{\frac{1}{{10k\Omega }} + \frac{1}{{1.74k\Omega }} + \frac{1}{{22.6k\Omega }}}} = 0.5V\label{52}\tag{52}$$

The current limit is set to:

$$I_{limit}= \frac{V_{Iset}}{40 \cdot R_{21}} = \frac{0.5V}{40 \cdot 0.043 \Omega} = 290mA\label{53}\tag{53}$$

During External and OFF modes, SETILIMUSR pin is driven HiZ by the FPGA. The voltage at the ISET pin of IC27 is:

$$V_{Iset}= \frac {V_{cap} \cdot R_{255}}{R_{253} + R_{255}} = \frac{3.6V \cdot 22.6k \Omega }{10k \Omega + 22.6k \Omega} = 2.5V\label{54}\tag{54}$$

The current limit is set to:

$$I_{limit}= \frac {V_{Iset}}{40 \cdot R_{21}} = \frac {2.5V}{40 \cdot 0.043 \Omega} = 1.45A\label{55}\tag{55}$$

In both cases, ${I_{limit}}$ is allowed for a maximum time of:

$$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{170} = 21.7 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 102ms\label{56}\tag{56}$$

If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, IC21 turns off Q2. A hot swap retry is initiated after:

$$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 2.585s\label{57}\tag{57}$$

Soft Start is not used; C183 is a No Load.

If the current drops below ${I_{limit}}$ before ${t_{fault}}$, normal operation begins.

The current limited by equations \ref{53} and \ref{55} is shared by both positive and negative user power supplies. After considering the efficiency of the user supply stages, about 100mA is available for user in both supplies together, in USB Only mode. In External mode, the current/power limit for user is set in the User Voltage Supplies, as explained below.

6.4. User Voltage Supplies

The user power supplies (Fig. 26) use ADP1612 Switching Converter in Buck-Boost DC-to-DC topology. Main features:

Figure 26. User power supplies. figure_26._user_power_supplies

Since the op amps are included in negative feedback loops, the input pins voltages are equal:

$${V_{ + IC46A}} = \frac{{\frac{{{V_{OUT + \_USR}}}}{{{R_{188}}}} + \frac{{{V_{SET + \_USR}}}}{{{R_{193}}}}}}{{\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}}}} = {V_{ - IC46A}} = \frac{{\frac{{{V_{FB}}}}{{{R_{266}}}}}}{{\frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}}}\label{58}\tag{58}$$

$${V_{ + IC46B}} = \frac{{\frac{{{V_{OUT - \_USR}}}}{{{R_{187}}}} + \frac{{{V_{FB}}}}{{{R_{270}}}}}}{{\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}}}} = {V_{ - IC46B}} = \frac{{\frac{{{V_{SET - \_USR}}}}{{{R_{190}}}}}}{{\frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}}}\label{59}\tag{59}$$

The input impedances for the op amps are matched:

$$\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}} = \frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}\label{60}\tag{60}$$

$$\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}} = \frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}\label{61}\tag{61}$$

The user voltages are:

$$V_{OUT\;+\_USR}=V_{FB} \cdot \frac{R_{188}}{R_{266}} - V_{SET\;+\_USR} \cdot \frac{R_{188}}{R_{193}}=5.33V-4.87 \cdot V_{SET\;+\_USR}\label{62}\tag{62}$$

$$V_{OUT\;-\_USR}=-V_{FB} \cdot \frac{R_{187}}{R_{270}} + V_{SET\;-\_USR} \cdot \frac{R_{187}}{R_{190}}=-5.33V+4.87 \cdot V_{SET\;-\_USR}\label{63}\tag{63}$$

Where:

$${V_{FB}} = 1.235V\;typical\label{64}\tag{64}$$

IC43 (Fig. 18) generates the setting voltages in the range:

$$0 < V_{SET + \_USR},\; V_{SET - \_USR} < 1.2V\label{65}\tag{65}$$

Which would allow output voltages to be set in the ranges:

$$ - 0.51V \le {V_{SET + \_USR}} < 5.33V\label{66}\tag{66}$$

$$0.51V \ge \; V_{SET - \_USR} > - 5.33V\label{67}\tag{67}$$

The margins allow for compensating the components’ tolerances. After calibration, the WaveForms SW only allows the ranges 0 to +/-5V respectively. Even so, output voltages below absolute value of 0.5V are not guaranteed. With light loads, such voltages might exhibit significant ripple (~15mV).

Each supply can be disabled by the FPGA.

6.5. Internal Power Supplies

6.5.1. Analog Supplies

Analog supplies need to have very low ripple to prevent noise from coupling into analog signals. Ferrite beads are used to filter the remaining switching noise and to separate the power supplies that go to the main analog circuit blocks, to avoid crosstalk.

The 3.3V (Fig. 27) and 1.8V Fig. 28 analog power supplies are implemented around an ADP2138 Fixed Output Voltage, 800mA, 3MHz, Step-Down DC-to-DC converter. To insure low output voltage ripple a second LC filter is added and forced PWM mode is selected.

Figure 28. 1.8V internal analog power supply. figure_28._1.8v_internal_analog_power_supply

The -3.3V analog power supply (Fig. 29) is implemented with the ADP2301 Step-Down regulator in an inverting Buck-Boost configuration. See application Note AN-1083: Designing an Inverting Buck Boost Using the ADP2300 and ADP2301. The ADP2301 features:

The Output voltage is set with an external resistor divider from Vout to FB:

$$\frac{{{R_{180}}}}{{{R_{181}}}} = \;\frac{{ - {V_{out}} - {V_{ref}}}}{{{V_{ref}}}}\label{68}\tag{68}$$

Choosing $R_{181} = 10.2k{\text{\Omega }}$:

$$R_{180}= \frac{3.3V-0.8V}{0.8V} \cdot 10.2k \Omega = 31.87k \Omega \label{69}\tag{69}$$

Closest standard value is $R_{180} = 31.6k{\text{\Omega }}$

The 5.5V and -5.5V supplies Fig. 30 are created with a Sepic-Cuk topology, built around a single ADP1612 Step-Up DC-to DC converter. Both Sepic and Cuk converters are connected to the same switching pin of the regulator. Only the positive Sepic output is regulated, while the negative output tracks the positive one. This is an accepted behavior, since similar load currents are expected on both positive and negative rails.

Figure 30. ±5.5V internal analog supplies. figure_30._5.5v_internal_analog_supplies

The output current in a Sepic is discontinuous which results in a higher output ripple. To lower this ripple an additional output filter is added to the positive rail.

For more information see application note: AN-1106: An Improved Topology for Creating Split Rails from a Single Input Voltage.

Setting the Output Voltage:

$$\frac{{{R_{184}}}}{{{R_{185}}}} = \;\frac{{{V_{out}} - {V_{ref}}}}{{{V_{ref}}}}\label{70}\tag{70}$$

Choosing ${R_{185}} = 13.7k\Omega$:

$$R_{184}= \frac{5.5V-1.235V}{1.235V} \cdot 13.7k \Omega = 47.31k \Omega\label{71}\tag{71}$$

Closest standard value is ${R_{184}} = 47.5k\Omega$

6.5.2. Digital Supplies

The 1V digital supply (Fig. 31) is implemented with the ADP2120-1. It has a fixed 1V output voltage option and a ±1.5% output accuracy which makes it suitable for the FPGA internal power supply. It also features:

The 3.3V digital supply (Fig. 32) uses ADP2503-3.3 600mA, 2.5MHz Buck-Boost DC-to-DC Converter:

The main requirement for the 3.3V digital supply is the reverse current capability. When a user pin is overdriven the protection diode opens and back powers circuitry connected to this supply. If the back powered energy is higher than the used energy the regulator delivers it to its input, preventing the 3.3V from rising.

The 1.8V digital power supply (Fig. 33) is implemented with ADP2138-1.8 Fixed Output Voltage, 800mA, 3MHz, Step-Down DC-to-DC converter. This ensures a very small solution size due to the 3MHz switching frequency and the 1mm × 1.5 mm WLCSP package.

The ADP2138 also features:

6.6. Temperature Measurement

The Analog Discovery 2 uses the AD7415 Digital Output Temperature Sensor (Fig. 34). AD7415 main features are:

The USB interface performs two tasks:

8. FPGA

The core of the Analog Discovery 2 is the Xilinx Spartan-6 FPGA circuit XC6SLX16-1L. The configured logic performs:

Block and Distributed RAM of the FPGA are used for signal synthesis and acquisition. Multiple configuration files are available through the WaveForms software to allocate the RAM resources according to the application.

Detail of the trigger system is shown in Fig. 35. Each instrument generates a trigger signal when a trigger condition is met. Each trigger signal (including external triggers) can trigger any instrument and drive the external trigger outputs. This way, all the instruments can synchronize to each other.

Figure 35. FPGA configuration trigger block diagram.

//{{anchor:figure_35:Figure 35. FPGA configuration trigger block diagram.}}//

9. Features and Performances

This chapter shows the features and performances as described in the Analog Discovery 2 Datasheet. Footnotes add detailed information and annotate the HW description in this Manual.

9.1. Analog Inputs (Scope)

9.2. Analog Outputs (Arbitrary Waveform Generator)

9.4. Digital Pattern Generator

9.5. Digital I/O

9.6. Power Supplies

9.7. Network Analyzer*³

9.8. Voltmeters°

9.9. Spectrum Analyzer°°

9.10. Other features

1) , 3) , 5) These 16 digital lines are shared by the Logic Analyzer, Pattern Generator and Digital I/O. They are always inputs, some of them can be set to be outputs also. Digital I/O has precedence in case of output conflict with the Pattern Generator.
2) , 4) , 6) , 7) When inputs, these lines can be set to be 1.8V CMOS compatible.
8) See note in section 2. Scope
9) High Gain: ±2.6V differential input voltage range.
10) Low Gain: ±29V differential input voltage range.
11) High Gain or Low Gain is used in the analog signal input path for rough scaling. “Digital Zooming” is used for multiple scope scales.
12) , 13) The Scope bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances (see Figure 21, down). With coax probes and Analog Discovery BNC adapter, the 0.5dB Scope bandwidth is 10 MHz (see Fig. 15).
14) As shown in Fig. 12, a ±50V differential input signal does not fit in a single scope screen (ADC range). However, Vertical Position setting allows visualization of either +50V or -50V levels.
15) Default Scope buffer size is 8kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resource allocation. With no memory allocated to the Digital I/O and reduced memory assigned to the AWG, the scope buffer size can be chosen to be 16kSamples/channel.
16) , 17) , 34) , 35) , 62) , 63) Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/outputs, cross-triggering between multiple Analog Discovery devices is possible.
18) Real time sampling modes are implemented in the FPGA. The ADC always works at 100Msamples/sec. When a lower sampling rate is required, (108/N samples/sec), N ADC samples are used to build a single recorded sample, either by averaging or decimating. In the Min/Max mode, every 2N samples are used to calculate and store a pair of Min/Max values. The stored sample rate is reduced by half in Min/Max mode.
19) In mixed signal mode, the scope and Digital I/O acquisition blocks use the same reference clock, for synchronization.
20) , 21) , 36) This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.
22) , 23) , 31) , 37) , 41) , 42) , 44) , 45) , 51) , 52) , 53) , 54) , 55) , 56) , 57) , 58) , 59) , 60) , 61) , 64) , 65) This functionality is implemented by WaveForms software, in the PC.
24) The AWG DAC always works at 100Msamples/sec. When a lower sampling rate is required, (108/N samples/sec), each sample is sent N times to the DAC.
25) , 26) The AWG output voltage is limited to ±5V. This refers to the sum of AC signal and DC offset.
27) , 28) The AWG bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances. With coax probes and Analog Discovery BNC adapter, the 0.5dB AWG bandwidth is 4MHz (see Figure 21).
29) Default AWG buffer size is 4kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resources allocation. With no memory allocated to the Digital I/O and reduced memory assigned to the Scope, the AWG buffer size can be 16kSamples/channel.
30) , 39) Real time implemented in the FPGA configuration.
32) , 38) , 43) All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.
33) Default Logic Analyzer buffer size is 4kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resource allocation. With no memory allocated to the Scope and AWG, the Logic Analyzer buffer size can be chosen to be 16kSamples/channel.
40) Default Pattern Generator buffer size is 1kSamples/channel. The WaveForms Device Manager provides alternate FPGA configuration files, with different resources allocation. With no memory allocated to the Scope and AWG, the Pattern Generator buffer size can be 16kSamples/channel.
46) WaveForms allows setting the user voltages in the range 0V…5V respectively -0V…-5V. However, voltages below 0.5V, respectively above -0.5V might have excessive ripple and should be used with caution.
47) This limit results from the overall device power balance: the power available from the USB port, minus the power internally used by the device, moderated by the user power supplies efficiency. The balance of 500mW is available for both user supplies to share.
48) , 49) , 50) This limit results from the structure of each user power supply (positive and negative). It is not conditioned by the load degree of the complementary user supply.