====流水灯设计文件====
<code verilog>
// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Module: Water_led
// 
// Author: Step
// 
// Description: Water_led
// 
// Web: www.ecbcamp.com
// 
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date:   |Changes Made:
// V1.0     |2015/11/11   |Initial ver
// --------------------------------------------------------------------
module Water_led #
(
parameter CNT_NUM = 25000000
)
(
input clk_in,
input rst_n_in,
output reg [7:0] led_out
);

reg [24:0] cnt = 25'd0;
always@(posedge clk_in or negedge rst_n_in) begin
	if(!rst_n_in) begin
		cnt <= 25'd0;
	end else if(cnt>=CNT_NUM-1) begin
		cnt <= 25'd0;
	end else begin
		cnt <= cnt + 25'd1;
	end
end

reg [3:0] led_cnt = 4'd0;
always@(posedge clk_in or negedge rst_n_in) begin
	if(!rst_n_in) begin
		led_cnt <= 4'd0;
	end else if(cnt==CNT_NUM-1) begin
		if(led_cnt==4'd7) led_cnt <= 4'd0;
		else led_cnt <= led_cnt + 4'd1;
	end
end

always@(led_cnt) begin
	case(led_cnt)
		4'd0: led_out = 8'b1111_1110;
		4'd1: led_out = 8'b1111_1101;
		4'd2: led_out = 8'b1111_1011;
		4'd3: led_out = 8'b1111_0111;
		4'd4: led_out = 8'b1110_1111;
		4'd5: led_out = 8'b1101_1111;
		4'd6: led_out = 8'b1011_1111;
		4'd7: led_out = 8'b0111_1111;
		default: led_out = 8'b1111_1111;
	endcase
end

endmodule
</code>