###Testing / Verification

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####项目
[[https://opencores.org/projects/boost_converter|Boost Converter]]\\
[[https://opencores.org/projects/bustap-jtag|Bus Transaction Monitor with JTAG]]\\
[[https://opencores.org/projects/fli|c - VHDL Co-Simulation with FLI]]\\
[[https://opencores.org/projects/crtg|Constrained random test generator]]\\
[[https://opencores.org/projects/astron_diagnostics|Diagnostics library]]\\
[[https://opencores.org/projects/ds1621|DS1621 model]]\\
[[https://opencores.org/projects/ezidebug|EziDebug]]\\
[[https://opencores.org/projects/fpo|FPO (Logic Analyzer)]]\\
[[https://opencores.org/projects/workwithfiles|FROM and TO files]]\\
[[https://opencores.org/projects/ahb_master|Generic AHB master stub]]\\
[[https://opencores.org/projects/ahb_slave|Generic AHB slave stub]]\\
[[https://opencores.org/projects/apb_mstr|Generic APB master stub]]\\
[[https://opencores.org/projects/apb_slave|Generic APB slave stub]]\\
[[https://opencores.org/projects/axi_master|Generic AXI master stub]]\\
[[https://opencores.org/projects/axi_slave|Generic AXI slave stub]]\\
[[https://opencores.org/projects/hasm|HASM TestBench Vector Generator]]\\
[[https://opencores.org/projects/highload|High Load configurable test project]]\\
[[https://opencores.org/projects/i2clcd|i2clcd]]\\
[[https://opencores.org/projects/logicprobe|LogicProbe]]\\
[[https://opencores.org/projects/oc_axi_bfm|Open Cores AXI Bus Functional Model for Intel Platform Designer/Altera-ModelSim]]\\
[[https://opencores.org/projects/openjtag-project|Open JTAG project]]\\

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[[https://opencores.org/projects/pltbutils|PlTbUtils]]\\
[[https://opencores.org/projects/prbs_suite|PRBS Signal Generator and Checker]]\\
[[https://opencores.org/projects/astron_sim_tools|Simulation tools library]]\\
[[https://opencores.org/projects/socexplorer|SocExplorer]]\\
[[https://opencores.org/projects/socgen|socgen]]\\
[[https://opencores.org/projects/sftb|Soundfile Testbench]]\\
[[https://opencores.org/projects/jtag_stapl_player|StaplPlayer]]\\
[[https://opencores.org/projects/sv_dir_tb|SystemVerilog Directed Test Bench]]\\
[[https://opencores.org/projects/vhld_tb|The VHDL Test Bench]]\\
[[https://opencores.org/projects/uart_observer|UART observer]]\\
[[https://opencores.org/projects/uart2bus_testbench|Uart2BusTestBench]]\\
[[https://opencores.org/projects/vhdl_wb_tb|VHDL Whisbone Test Bench]]\\
[[https://opencores.org/projects/patterngen|Video Pattern Generator]]\\
[[https://opencores.org/projects/wbscope|Wishbone Scope]]\\