###System on Chip \\ ####项目 [[https://opencores.org/projects/dma_ahb|AHB DMA 32 / 64 bits]]\\ [[https://opencores.org/projects/ahb_system_generator|ahb system generator]]\\ [[https://opencores.org/projects/ahb2wishbone|AHB to Wishbone Bridge]]\\ [[https://opencores.org/projects/aoocs|aoOCS - Wishbone Amiga OCS SoC]]\\ [[https://opencores.org/projects/core_arm|Arm core]]\\ [[https://opencores.org/projects/avuc|Assembler with VHDL User-defined Commands (AVUC)]]\\ [[https://opencores.org/projects/async_sdm_noc|Async-SDM-NoC]]\\ [[https://opencores.org/projects/dma_axi|AXI DMA 32 / 64 bits]]\\ [[https://opencores.org/projects/axi4_tlm_bfm|AXI4 Transactor and Bus Functional Model]]\\ [[https://opencores.org/projects/ccsds_rxtxsoc|CCSDS RX_TX_SoC]]\\ [[https://opencores.org/projects/s6soc|CMOD S6 SoC]]\\ [[https://opencores.org/projects/cpu_lecture|CPU Lecture]]\\ [[https://opencores.org/projects/eco32|ECO32]]\\ [[https://opencores.org/projects/embedded_risc|Embedded 32-bit RISC uProcessor with SDRAM Controller]]\\ [[https://opencores.org/projects/fpga|Embedded FPGA Core]]\\ [[https://opencores.org/projects/epc_rfid_transponder|EPC RFID Transponder]]\\ [[https://opencores.org/projects/xucpu|Experimental Unstable CPU]]\\ \\ [[https://opencores.org/projects/gecko3|GECKO3 SoC co-design environment]]\\ [[https://opencores.org/projects/gecko4|GECKO4 SoC co-design environment]]\\ [[https://opencores.org/projects/robust_ahb_matrix|Generic AHB matrix]]\\ [[https://opencores.org/projects/robust_reg|Generic APB register file]]\\ [[https://opencores.org/projects/axi_dma|Generic AXI DMA]]\\ [[https://opencores.org/projects/robust_axi_fabric|Generic AXI interconnect fabric]]\\ [[https://opencores.org/projects/robust_axi2ahb|Generic AXI to AHB bridge]]\\ [[https://opencores.org/projects/robust_axi2apb|Generic AXI to APB bridge]]\\ [[https://opencores.org/projects/forth-cpu|H2 Forth SoC]]\\ [[https://opencores.org/projects/i2c_wb_wrapper|I2C Controller Wishbone Wrapper]]\\ [[https://opencores.org/projects/efficent_integrated_round_robin_arbiter|Integrated round robin arbiter]]\\ [[https://opencores.org/projects/soc_auto_vbus|Internal communication bus for FPGA]]\\ [[https://opencores.org/projects/keras_to_fpga|Keras to FPGA]]\\ [[https://opencores.org/projects/layer2|layer[2]]\\ [[https://opencores.org/projects/m16c5x|M16C5x]]\\ [[https://opencores.org/projects/masocist|MaSoCist Soc builder/simulator]]\\ \\ [[https://opencores.org/projects/minsoc|minsoc]]\\ [[https://opencores.org/projects/decoder|MP3 decoder]]\\ [[https://opencores.org/projects/next186_soc_pc|Next186 SoC PC]]\\ [[https://opencores.org/projects/next186mp3|Next186MP3]]\\ [[https://opencores.org/projects/an-fpga-implementation-of-low-latency-noc-based-mpsoc|NoC based MPSoC]]\\ [[https://opencores.org/projects/noc|NoC(Network-on-Chip) Simulator]]\\ [[https://opencores.org/projects/nocem|NoCem -- Network on Chip emulator]]\\ [[https://opencores.org/projects/nocmodel|NoCmodel]]\\ [[https://opencores.org/projects/oc-h264-encoder|OC - H.264 Encoder SoC]]\\ [[https://opencores.org/projects/oms8051mini|OMS8051 MINI]]\\ [[https://opencores.org/projects/opencl_bsp_nallatech_bittware_385a_40g_ethernet|OpenCL Board Support Package (BSP) for the Nallatech / Bittware 385A including dual 40 Gigabit Ethernet interfaces.]]\\ [[https://opencores.org/projects/openfire2|OpenFIRE]]\\ [[https://opencores.org/projects/sparc64soc|OpenSPARC-based SoC]]\\ [[https://opencores.org/projects/or1200_soc|or1200_soc]]\\ [[https://opencores.org/projects/or1k_soc_on_altera_embedded_dev_kit|Or1k SoC on Altera Embedded Dev Kit]]\\ [[https://opencores.org/projects/orpsoc|ORPSoC]]\\ [[https://opencores.org/projects/pdp1|PDP-1 reimplementation]]\\ [[https://opencores.org/projects/pif2wb|PIF2WB]]\\ [[https://opencores.org/projects/plbv46_to_wb_bridge|PLBv46 to Wishbone Bridge]]\\ [[https://opencores.org/projects/oberon_sdram|Project Oberon with SDRAM]]\\ [[https://opencores.org/projects/pss|PSS (Programmable Supervisor for Systems-on-Chip)]]\\ [[https://opencores.org/projects/image_component_labeling_and_feature_extraction|Real-time image processing]]\\ [[https://opencores.org/projects/rfid|rfid tag and reader]]\\ [[https://opencores.org/projects/rtf68ksys|rtf68kSys]]\\ [[https://opencores.org/projects/sardmips|SardMIPS]]\\ [[https://opencores.org/projects/simple_bus_architecture|SBA - Simple Bus Architecture]]\\ [[https://opencores.org/projects/simpcon|SimpCon - a Simple SoC Interconnect]]\\ [[https://opencores.org/projects/ax4lbr|Simple AXI4-Lite bridges for IPbus and Wishbone]]\\ [[https://opencores.org/projects/mpdma|Soft MultiProcessor on FPGA]]\\ [[https://opencores.org/projects/storm_soc|STORM SoC]]\\ [[https://opencores.org/projects/riscv_vhdl|System-On-Chip based on bare Rocket-chip (RISC-V ISA)]]\\ [[https://opencores.org/projects/socwire|System-on-Chip Wire (SoCWire)]]\\ [[https://opencores.org/projects/system05|system05]]\\ [[https://opencores.org/projects/system09|System09]]\\ [[https://opencores.org/projects/taar|Taar Microprocessor]]\\ [[https://opencores.org/projects/opb_wb_wrapper|WB/OPB & OPB/WB Interface Wrapper]]\\ [[https://opencores.org/projects/wb_builder|WISHBONE Builder]]\\ [[https://opencores.org/projects/wb_conbus|WISHBONE Conbus IP Core]]\\ [[https://opencores.org/projects/wb_conmax|WISHBONE Conmax IP Core]]\\ [[https://opencores.org/projects/wb_dma|WISHBONE DMA/Bridge IP Core]]\\ [[https://opencores.org/projects/wishbone_out_port|wishbone out port from b3 spec]]\\ [[https://opencores.org/projects/system6801|Wishbone System6800/01]]\\ [[https://opencores.org/projects/wisbone_2_ahb|Wishbone to AHB Bridge]]\\ [[https://opencores.org/projects/wb_tk|WishboneTK toolkit]]\\ [[https://opencores.org/projects/xulalx25soc|XuLA2-LX25 SoC]]\\ [[https://opencores.org/projects/z80soc|Z80 System on Chip]]\\ [[https://opencores.org/projects/zorro_to_wishbone_bridge|Zorro bus to Wishbone bridge]]\\