assign  key_edge = key_rst_pre & (~key_rst);//脉冲边沿检测。当key检测到下降沿时，key_edge产生一个时钟周期的高电平

always @(posedge clk  or  negedge rst)
    begin
        if (!rst) 
        key_sec <= {N{1'b1}};                
    else if (cnt==18'h3ffff)
        key_sec <= key;  
    end
    always @(posedge clk  or  negedge rst)
        begin
            if (!rst)
                key_sec_pre <= {N{1'b1}};
            else                   
                key_sec_pre <= key_sec;             
        end      
    assign  key_pulse = key_sec_pre & (~key_sec);