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2024年寒假练 - 基于小脚丫FPGA套件STEP BaseBoard V4.0实现一个rtc闹钟
该项目使用了小脚丫FPGA套件STEP BaseBoard V4.0，实现了rtc闹钟的设计，它的主要功能为：实时时钟+闹钟。
标签
FPGA
小脚丫
wakojosin
更新2024-03-29
221

1. 项目需求

项目的基本要求是设计一个能够显示时、分、秒钟的数字时钟，时间在7段数码管上显示。自定义扩展板上的矩阵按键调整数字时钟的时间并设定定时报警的时间，分别用四个键来控制分、时的增、减，将设定好的定时时间存储在EEPROM中，断电并再次上电以后（需要重新再调整当前时钟的时间）能够根据上次设定的定时报警的时间进行报警，到报警时间时蜂鸣器播放音乐5秒钟、核心板上的一颗RGB LED以呼吸灯的方式闪烁5秒钟，闪烁的过程中通过R、G、B颜色的不同组合显示不同颜色（类似警灯的效果）。

扩展要求是通过WIFI进行时间同步，时间在数码管和lcd上显示等。


2.需求分析

从项目的要求中可以得到基本的需求是通过计数器来实现一个支持时分秒计时的数字时钟，时间在数码管上显示，通过按键进行时间和闹钟的设置，通过rgb led和蜂鸣器进行报警提醒。扩展功能则是在基础功能上增加网络时钟接收和lcd显示。

而我的实现根据手里的资源和自身的要求，对数字闹钟的实现做了一点改动，主要功能是通过类spi的串型总线与rtc芯片（HT1302）通讯获取时间信息，同时也支持串型总线对rtc进行时间的设置，然后闹钟时间是保存在eeprom中，闹钟触发后，通过rgb led呼吸灯和蜂鸣器进行报警。时间的设置支持年月日时分秒，通过按键进行翻页和滚动显示。


3.实现的方式

下面来介绍一下整体的功能实现。

首先是输入部分，由7个按键进行闹钟的所有功能操作，按键定义如下：

按键1为left键，主要用于向左滚动显示；

按键2为up键，主要用于向上翻页；

按键3为down键，主要用于向下翻页；

按键4为right键，主要用于向右滚动显示；

按键5为ok键，用于确认设置；

按键6/7为add/sub键，用于时间参数的调整；

按键8为cannel键，目前未定义功能；

按键9~16为调试按键，用于通过led输出中间状态信息；


输出部分由数码管负责，数码管最左边两位用于显示页码，后面的内容是显示具体的数据。

当前的页面定义一共有3页，分别是：

页面1为时钟显示页，可以实时显示RTC的年月日时分秒；

页面2为时钟配置页，用于设置RTC的时间参数；

页面3为闹钟设置页，用于设置闹钟的触发时间；


剩下的功能模块主要有RTC控制逻辑、EEPROM控制逻辑、蜂鸣器逻辑和rgbled的pwm控制逻辑。


4.功能框图

image.png


5.代码（内嵌到报告中）及说明

首先介绍控制中心的代码，这部分分为按键扫描、翻页控制、内容显示等部分，下面是代码：

5.1按键检测及处理

        /*left key*/
        if({key_left,key_left_r}==2'b10) begin
            key_left_r  <= 1'b1;
        end
        /*right key*/
        if({key_right,key_right_r}==2'b10) begin
            key_right_r <= 1'b1;
        end
        /*up key*/
        if({key_up,key_up_r}==2'b10) begin
            key_up_r     <= 1'b1;
        end
        /*down key*/
        if({key_down,key_down_r}==2'b10) begin
            key_down_r   <= 1'b1;
        end
        /*ok key*/
        if({key_ok,key_ok_r}==2'b10) begin
            key_ok_r <= 1'b1;
        end
        /*add key*/
        if({key_add,key_add_r}==2'b10) begin
            key_add_r <= 1'b1;
        end
        /*sub key*/
        if({key_sub,key_sub_r}==2'b10) begin
            key_sub_r <= 1'b1;
        end
        /*cancel key*/
        if({key_cancel,key_cancel_r}==2'b10) begin
            key_cancel_r <= 1'b1;
        end

5.2翻页控制

        /*page process*/
        if(main_sm<MAIN_SM_PAGE1) begin
            /*page protect.*/
        end else begin
            if({key_up,key_up_r}==2'b01) begin
                key_up_r     <= 1'b0;
                page_update  <= 1'b1;
                if(main_sm == MAIN_SM_PAGE1) begin
                    main_sm <= MAIN_SM_PAGE3;
                end else begin
                    main_sm <= main_sm - 1'b1;
                end
                if(offset<4'd11) offset <= offset + 1'b1;
                else offset <= offset;
            end
            if({key_down,key_down_r}==2'b01) begin
                key_down_r   <= 1'b0;
                page_update  <= 1'b1;
                if(main_sm == MAIN_SM_PAGE3) begin
                    main_sm <= MAIN_SM_PAGE1;
                end else begin
                    main_sm <= main_sm + 1'b1;
                end
            end
        end

5.3各页面内容显示部分

这部分内容比较多，包含了各个页面的显示内容处理及中间过渡的数据处理等，代码的说明就放在注释里面了：

5.3.1页面切换


        if(page_update==1'b1) begin // 这里表示发生了页面切换
            page_update        <= 1'b0;
            offset             <= 4'd0;
            digiseg_blink_mask <= 8'd0;
            main_ssm           <= 4'd0;
            case(main_sm)
            default        : rtc_en <= 1'b0;
            MAIN_SM_PAGE1  : rtc_en <= 1'b1; //这里是RTC显示页面，需要开启RTC
            MAIN_SM_PAGE2  : begin //这里是时间设置页面，先关闭RTC，并将当前时间加载到缓存中
                rtc_en <= 1'b0;
                time_year_r <= rtc_year;
                time_mon_r  <= rtc_mon;
                time_day_r  <= rtc_day;
                time_hour_r <= rtc_hour;
                time_min_r  <= rtc_min;
                time_sec_r  <= rtc_sec;
            end
            MAIN_SM_PAGE3  : begin //这里是闹钟设置页面，关闭RTC，并将当前的闹钟时间加载到缓存中
                rtc_en <= 1'b0;
                if(alarm_sec_r!=8'hFF) begin
                    time_year_r <= alarm_year_r;
                    time_mon_r  <= alarm_mon_r ;
                    time_day_r  <= alarm_day_r ;
                    time_hour_r <= alarm_hour_r;
                    time_min_r  <= alarm_min_r ;
                    time_sec_r  <= alarm_sec_r ;
                end else begin //无效的闹钟时间，不加载
                    time_year_r <= 8'd0;
                    time_mon_r  <= 8'd1;
                    time_day_r  <= 8'd1;
                    time_hour_r <= 8'd0;
                    time_min_r  <= 8'd0;
                    time_sec_r  <= 8'd0;
                end
            end
            endcase
        end else begin //展开内容在后面
        end

5.3.2页面显示


            case(main_sm)
            MAIN_SM_STARTUP: begin //上电初始化，主要干了从EEPROM读取闹钟时间的事情。
                /*load param from eprom*/
                case(main_ssm)
                4'd0: begin
                    /*
                    step:
                    set data(write only) and dir;
                    set en;
                    wait busy to 1;
                    wait ready to 1;
                    clear en;
                    wait all stat to 0;
                    */
                    eprom_rtc_dir <= 1'b1; /*read*/
                    main_ssm      <= main_ssm + 1'b1;
                    main_sm       <= main_sm;
                end
                4'd1: begin
                    eprom_rtc_en <= 1'b1; /*reading*/
                    main_ssm     <= main_ssm + 1'b1;
                    main_sm      <= main_sm;
                end
                4'd2: begin
                    /*wait busy*/
                    if(eprom_rtc_stat_busy==1'b1) begin
                        main_ssm <= main_ssm + 1'b1;
                    end else begin
                        main_ssm <= main_ssm;
                    end
                    main_sm <= main_sm;
                end
                4'd3: begin
                    /*wait ready*/
                    if(eprom_rtc_stat_ready==1'b1) begin
                        main_ssm <= main_ssm + 1'b1;
                        /*check*/
                        if(eprom_rtc_stat_check==1'b1) begin
                            alarm_year_r <= eprom_rtc_year;
                            alarm_mon_r  <= eprom_rtc_mon;
                            alarm_day_r  <= eprom_rtc_day;
                            alarm_hour_r <= eprom_rtc_hour;
                            alarm_min_r  <= eprom_rtc_min;
                            alarm_sec_r  <= eprom_rtc_sec;
                        end else begin
                            alarm_sec_r  <= 8'hFF;
                        end
                    end else begin
                        main_ssm <= main_ssm;
                    end
                    main_sm <= main_sm;
                end
                4'd4: begin
                    eprom_rtc_en <= 1'b0;
                    main_ssm     <= 4'd0;
                    main_sm      <= MAIN_SM_PAGE1;
                    page_update  <= 1'b1;
                end
                endcase
            end
            MAIN_SM_RTC_SET: begin //设置RTC时间，通过操作流程将设置的时间写入RTC
                case(offset)
                4'd0: begin
                    rtc_wren_r <= 1'b1;
                    offset     <= offset + 1'b1;
                end
                4'd1: begin
                    rtc_en <= 1'b1;
                    offset <= offset + 1'b1;
                end
                4'd2: begin
                    if(rtc_wrbusy==1'b1) begin
                        offset <= offset + 1'b1;
                        rtc_en <= 1'b0;
                    end
                end
                4'd3: begin
                    if(rtc_wrbusy==1'b0) begin
                        rtc_wren_r    <= 1'b0;
                        page_update   <= 1'b1;
                        main_sm       <= MAIN_SM_PAGE1;
                    end
                end
                endcase
            end
            MAIN_SM_ALARM_SAVE: begin //闹钟设置，将闹钟时间写入EEPROM，同时同步到当前闹钟时间中
                /*load param from eprom*/
                case(main_ssm)
                4'd0: begin
                    /*
                    step:
                    set data(write only) and dir;
                    set en;
                    wait busy to 1;
                    wait ready to 1;
                    clear en;
                    wait all stat to 0;
                    */
                    eprom_rtc_dir <= 1'b0; /*write*/
                    main_ssm      <= main_ssm + 1'b1;
                    main_sm       <= main_sm;
                end
                4'd1: begin
                    eprom_rtc_en <= 1'b1; /*writing*/
                    main_ssm     <= main_ssm + 1'b1;
                    main_sm      <= main_sm;
                end
                4'd2: begin
                    /*wait busy*/
                    if(eprom_rtc_stat_busy==1'b1) begin
                        main_ssm <= main_ssm + 1'b1;
                    end else begin
                        main_ssm <= main_ssm;
                    end
                    main_sm <= main_sm;
                end
                4'd3: begin
                    /*wait ready*/
                    if(eprom_rtc_stat_ready==1'b1) begin
                        main_ssm <= main_ssm + 1'b1;
                        /*write without check*/
                        alarm_year_r <= eprom_rtc_year_r;
                        alarm_mon_r  <= eprom_rtc_mon_r;
                        alarm_day_r  <= eprom_rtc_day_r;
                        alarm_hour_r <= eprom_rtc_hour_r;
                        alarm_min_r  <= eprom_rtc_min_r;
                        alarm_sec_r  <= eprom_rtc_sec_r;
                    end else begin
                        main_ssm <= main_ssm;
                    end
                    main_sm <= main_sm;
                end
                4'd4: begin
                    eprom_rtc_en <= 1'b0;
                    main_ssm     <= 4'd0;
                    main_sm      <= MAIN_SM_PAGE1;
                    page_update  <= 1'b1;
                end
                endcase
            end
            MAIN_SM_PAGE1: begin // 显示页面1，当前时间
                if({key_left,key_left_r}==2'b01) begin //滚动显示控制
                    key_left_r <= 1'b0;
                    if(offset==4'd0) offset <= 4'd1;
                    else offset <= offset;
                end else if({key_right,key_right_r}==2'b01) begin
                    key_right_r <= 1'b0;
                    if(offset==4'd1) offset <= 4'd0;
                    else offset <= offset;
                end
                time_year_r <= rtc_year;
                time_mon_r  <= rtc_mon;
                time_day_r  <= rtc_day;
                time_hour_r <= rtc_hour;
                time_min_r  <= rtc_min;
                time_sec_r  <= rtc_sec;
                if(offset==4'd0) begin
                    digiseg_fb[0] <= {2'd0,time_sec_r[3:0] };/*sec_l*/
                    digiseg_fb[1] <= {2'd0,time_sec_r[7:4] };/*sec_h*/
                    digiseg_fb[2] <= {2'd0,time_min_r[3:0] };/*min_l*/
                    digiseg_fb[3] <= {2'd0,time_min_r[7:4] };/*min_h*/
                    digiseg_fb[4] <= {2'd0,time_hour_r[3:0]};/*hour_l*/
                    digiseg_fb[5] <= {2'd0,time_hour_r[7:4]};/*hour_h*/
                end else begin
                    digiseg_fb[0] <= {2'd0,time_day_r[3:0] };
                    digiseg_fb[1] <= {2'd0,time_day_r[7:4] };
                    digiseg_fb[2] <= {2'd0,time_mon_r[3:0] };
                    digiseg_fb[3] <= {2'd0,time_mon_r[7:4] };
                    digiseg_fb[4] <= {2'd0,time_year_r[3:0]};
                    digiseg_fb[5] <= {2'd0,time_year_r[7:4]};
                end
                digiseg_fb[6] <= 6'h10;/*-*/
                digiseg_fb[7] <= 6'd1;/*page*/
            end
            default: begin // 这里是时间设置和闹钟设置，对于键盘进行时间调整的过程是重复的，所以整合在一起了
                /*time setting*/
                if({key_left,key_left_r}==2'b01) begin
                    key_left_r         <= 1'b0;
                    if(offset<4'd11) offset <= offset + 1'b1;
                    else offset <= offset;
                end else if({key_right,key_right_r}==2'b01) begin
                    key_right_r        <= 1'b0;
                    if(offset>4'd0) offset <= offset - 1'b1;
                    else offset  <= offset;
                end else if({key_add,key_add_r}==2'b01) begin
                    key_add_r <= 1'b0;
                    /*add time*/
                    case(offset)
                    /*hh/mm/ss*/
                    4'd0: begin
                        if(time_sec_r<8'h59) begin
                            if(time_sec_r[3:0]<4'd9) time_sec_r[3:0] <= time_sec_r[3:0]+1'b1;
                            else time_sec_r <= {time_sec_r[7:4]+1'b1, 4'd0};
                        end else begin
                            time_sec_r <= 8'd0;
                        end
                    end
                    4'd1: begin
                        if(time_sec_r<8'h50) time_sec_r[7:4] <= time_sec_r[7:4]+1'b1;
                        else time_sec_r <= 8'd0;
                    end
                    4'd2: begin
                        if(time_min_r<8'h59) begin
                            if(time_min_r[3:0]<4'd9) time_min_r[3:0] <= time_min_r[3:0]+1'b1;
                            else time_min_r <= {time_min_r[7:4]+1'b1, 4'd0};
                        end else begin
                            time_min_r <= 8'h00;
                        end
                    end
                    4'd3: begin
                        if(time_min_r<8'h50) time_min_r[7:4] <= time_min_r[7:4]+1'b1;
                        else time_min_r <= 8'h00;
                    end
                    4'd4: begin
                        if(time_hour_r<8'h23) begin
                            if(time_hour_r[3:0]<4'd9) time_hour_r[3:0] <= time_hour_r[3:0]+1'b1;
                            else time_hour_r <= {time_hour_r[7:4]+1'b1, 4'd0};
                        end else begin
                            time_hour_r <= 8'h00;
                        end
                    end
                    4'd5: begin
                        if(time_hour_r<8'h14) time_hour_r[7:4] <= time_hour_r[7:4]+1'b1;
                        else time_hour_r <= 8'h00;
                    end
                    /*yy/MM/dd*/
                    4'd6: begin
                        if(time_day_r<8'h31) begin
                            if(time_day_r[3:0]<4'd9) time_day_r[3:0] <= time_day_r[3:0]+1'b1;
                            else time_day_r <= {time_day_r[7:4]+1'b1, 4'd0};
                        end else begin
                            time_day_r <= 8'h01;
                        end
                    end
                    4'd7: begin
                        if(time_day_r<8'h22) time_day_r[7:4] <= time_day_r[7:4]+1'b1;
                        else time_day_r <= 8'h01;
                    end
                    4'd8: begin
                        if(time_mon_r<8'h12) begin
                            if(time_mon_r[3:0]<4'd9) time_mon_r[3:0] <= time_mon_r[3:0]+1'b1;
                            else time_mon_r <= {time_mon_r[7:4]+1'b1, 4'd0};
                        end else begin
                            time_mon_r <= 8'h01;
                        end
                    end
                    4'd9: begin
                        if(time_mon_r<8'h03) time_mon_r[7:4] <= time_mon_r[7:4]+1'b1;
                        else time_mon_r <= 8'h01;
                    end
                    4'd10: begin
                        if(time_year_r<8'h99) begin
                            if(time_year_r[3:0]<4'd9) time_year_r[3:0] <= time_year_r[3:0]+1'b1;
                            else time_year_r <= {time_year_r[7:4]+1'b1, 4'd0};
                        end else begin
                            time_year_r <= 8'h00;
                        end
                    end
                    4'd11: begin
                        if(time_year_r<8'h90) time_year_r[7:4] <= time_year_r[7:4]+1'b1;
                        else time_year_r <= 8'h00;
                    end
                    endcase
                end else if({key_sub,key_sub_r}==2'b01) begin
                    key_sub_r <= 1'b0;
                    /*sub time*/
                    case(offset)
                    /*hh/mm/ss*/
                    4'd0: begin
                        if(time_sec_r[3:0] > 4'h0) time_sec_r[3:0] <= time_sec_r[3:0]-1'b1;
                        else if(time_sec_r[7:4] > 4'h0) time_sec_r <= {time_sec_r[7:4]-1'b1, 4'h9};
                        else time_sec_r <= 8'h59;
                    end
                    4'd1: begin
                        if(time_sec_r>8'h9) time_sec_r[7:4] <= time_sec_r[7:4]-1'b1;
                        else time_sec_r <= 8'h59;
                    end
                    4'd2: begin
                        if(time_min_r[3:0] > 4'h0) time_min_r[3:0] <= time_min_r[3:0]-1'b1;
                        else if(time_min_r[7:4] > 4'h0) time_min_r <= {time_min_r[7:4]-1'b1, 4'h9};
                        else time_min_r <= 8'h59;
                    end
                    4'd3: begin
                        if(time_min_r>8'h9) time_min_r[7:4] <= time_min_r[7:4]-1'b1;
                        else time_min_r <= 8'h59;
                    end
                    4'd4: begin
                        if(time_hour_r[3:0] > 4'h0) time_hour_r[3:0] <= time_hour_r[3:0]-1'b1;
                        else if(time_hour_r[7:4] > 4'h0) time_hour_r <= {time_hour_r[7:4]-1'b1, 4'h9};
                        else time_hour_r <= 8'h23;
                    end
                    4'd5: begin
                        if(time_hour_r>8'h9) time_hour_r[7:4] <= time_hour_r[7:4]-1'b1;
                        else time_hour_r <= 8'h23;
                    end
                    /*yy/MM/dd*/
                    4'd6: begin
                        if(time_day_r[3:0] > 4'h0) time_day_r[3:0] <= time_day_r[3:0]-1'b1;
                        else if(time_day_r[7:4] > 4'h0) time_day_r <= {time_day_r[7:4]-1'b1, 4'h9};
                        else time_day_r <= 8'h31;
                    end
                    4'd7: begin
                        if(time_day_r>8'h10) time_day_r[7:4] <= time_day_r[7:4]-1'b1;
                        else time_day_r <= 8'h31;
                    end
                    4'd8: begin
                        if(time_mon_r[3:0] > 4'h0) time_mon_r[3:0] <= time_mon_r[3:0]-1'b1;
                        else if(time_mon_r[7:4] > 4'h0) time_mon_r <= {time_mon_r[7:4]-1'b1, 4'h9};
                        else time_mon_r <= 8'h12;
                    end
                    4'd9: begin
                        if(time_mon_r>8'h10) time_mon_r[7:4] <= time_mon_r[7:4]-1'b1;
                        else time_mon_r <= 8'h12;
                    end
                    4'd10: begin
                        if(time_year_r[3:0] > 4'h0) time_year_r[3:0] <= time_year_r[3:0]-1'b1;
                        else if(time_year_r[7:4] > 4'h0) time_year_r <= {time_year_r[7:4]-1'b1, 4'h9};
                        else time_year_r <= 8'h99;
                    end
                    4'd11: begin
                        if(time_year_r>8'h9) time_year_r[7:4] <= time_year_r[7:4]-1'b1;
                        else time_year_r <= 8'h99;
                    end
                    endcase
                end
                //上面是时间调整，下面是设置/保存操作。
                if({key_ok,key_ok_r}==2'b01) begin
                    key_ok_r    <= 1'b0;
                    if(main_sm==MAIN_SM_PAGE2) begin
                        /*apply time*/
                        page_update <= 1'b1;
                        main_sm     <= MAIN_SM_RTC_SET;
                        rtc_year_r  <= time_year_r;
                        rtc_wday_r  <= 8'd1;
                        rtc_mon_r   <= time_mon_r;
                        rtc_day_r   <= time_day_r;
                        rtc_hour_r  <= time_hour_r;
                        rtc_min_r   <= time_min_r;
                        rtc_sec_r   <= time_sec_r;
                    end else if(main_sm==MAIN_SM_PAGE3) begin
                        /*apply time*/
                        page_update      <= 1'b1;
                        main_sm          <= MAIN_SM_ALARM_SAVE;
                        eprom_rtc_year_r <= time_year_r;
                        eprom_rtc_wday_r <= 8'd1;
                        eprom_rtc_mon_r  <= time_mon_r;
                        eprom_rtc_day_r  <= time_day_r;
                        eprom_rtc_hour_r <= time_hour_r;
                        eprom_rtc_min_r  <= time_min_r;
                        eprom_rtc_sec_r  <= time_sec_r;
                        /*alarm setting*/
                    end
                end
                //后面是页面显示部分
                if(key_left_r|key_right_r==1'b1)begin
                    digiseg_blink_mask <= 8'd0;
                end else begin
                    if(offset < 6) begin
                        digiseg_fb[0] <= {2'd0,time_sec_r[3:0] };/*sec_l*/
                        digiseg_fb[1] <= {2'd0,time_sec_r[7:4] };/*sec_h*/
                        digiseg_fb[2] <= {2'd0,time_min_r[3:0] };/*min_l*/
                        digiseg_fb[3] <= {2'd0,time_min_r[7:4] };/*min_h*/
                        digiseg_fb[4] <= {2'd0,time_hour_r[3:0]};/*hour_l*/
                        digiseg_fb[5] <= {2'd0,time_hour_r[7:4]};/*hour_h*/
                        digiseg_blink_mask[offset] <= 1'b1;
                    end else begin
                        digiseg_fb[0] <= {2'd0,time_day_r[3:0] };
                        digiseg_fb[1] <= {2'd0,time_day_r[7:4] };
                        digiseg_fb[2] <= {2'd0,time_mon_r[3:0] };
                        digiseg_fb[3] <= {2'd0,time_mon_r[7:4] };
                        digiseg_fb[4] <= {2'd0,time_year_r[3:0]};
                        digiseg_fb[5] <= {2'd0,time_year_r[7:4]};
                        digiseg_blink_mask[offset-6] <= 1'b1;
                    end
                    if(main_sm==MAIN_SM_PAGE2) begin
                        /*time setting*/
                        digiseg_fb[6] <= 6'h10;/*-*/
                        digiseg_fb[7] <= 6'd2;/*page*/
                    end else if(main_sm==MAIN_SM_PAGE3) begin
                        /*alarm setting*/
                        digiseg_fb[6] <= 6'h10;/*-*/
                        digiseg_fb[7] <= 6'd3;/*page*/
                    end
                end
            end
            endcase

至于其他子模块的内容就不展开了，展开讲内容实在太多了，有兴趣的同学直接看源码吧。


6.仿真波形图

6.1EEPROM保存闹钟的仿真波形

image.png

6.2RTC仿真波形

image.png

6.3数码管仿真波形

image.png

主要的功能模块仿真就是这些，基本的符合预期的。


7.FPGA的资源利用说明

资源消耗情况如下截图，不太懂什么意思，没看到LUT之类的东西。PFU应该是类似的东西吧。

image.png

下面的是在线IDE输出的资源日志

Design Summary:
Number of registers: 856 out of 4635 (18%)
PFU registers: 856 out of 4320 (20%)
PIO registers: 0 out of 315 (0%)
Number of SLICEs: 1454 out of 2160 (67%)
SLICEs as Logic/ROM: 1454 out of 2160 (67%)
SLICEs as RAM: 0 out of 1620 (0%)
SLICEs as Carry: 184 out of 2160 (9%)
Number of LUT4s: 2881 out of 4320 (67%)
Number used as logic LUTs: 2513
Number used as distributed RAM: 0
Number used as ripple logic: 368
Number used as shift registers: 0
Number of PIO sites used: 36 + 4(JTAG) out of 105 (38%)
Number of block RAMs: 0 out of 10 (0%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 2 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 6
Net clk_c: 355 loads, 355 rising, 0 falling (Driver: PIO clk )
Net rtc_clkclk1_27 )
Net alarm_indicator_clk0clk1_27 )
Net clk_o_c: 33 loads, 0 rising, 33 falling (Driver: clk_100hz/clk1_27 )
Net kb_clkclk1_27 )
Net eeprom_rtc_alarm0clk1_27 )
Number of Clock Enables: 239
Net clk_c_enable_271: 25 loads, 25 LSLICEs
Net clk1_enable_72: 2 loads, 2 LSLICEs
Net clk_c_enable_47: 8 loads, 8 LSLICEs
Net clk_c_enable_264: 3 loads, 3 LSLICEs
Net ikey_0: 1 loads, 1 LSLICEs
Net ikey_3: 1 loads, 1 LSLICEs
Net ikey_1: 1 loads, 1 LSLICEs
Net ikey_2: 1 loads, 1 LSLICEs
Net ikey_4: 1 loads, 1 LSLICEs
Net ikey_5: 1 loads, 1 LSLICEs
Net clk_c_enable_174: 4 loads, 4 LSLICEs
Net clk_c_enable_168: 4 loads, 4 LSLICEs
Net clk_c_enable_162: 4 loads, 4 LSLICEs
Net clk_c_enable_156: 4 loads, 4 LSLICEs
Net clk_c_enable_150: 4 loads, 4 LSLICEs
Net clk_c_enable_143: 4 loads, 4 LSLICEs
Net clk_c_enable_137: 24 loads, 24 LSLICEs
Net clk_c_enable_107: 24 loads, 24 LSLICEs
Net clk_c_enable_64: 8 loads, 8 LSLICEs
Net en_r_N_956: 1 loads, 1 LSLICEs
Net clk_c_enable_236: 3 loads, 3 LSLICEs
Net clk_c_enable_254: 4 loads, 4 LSLICEs
Net rst_n_c: 9 loads, 9 LSLICEs
Net clk_c_enable_301: 2 loads, 2 LSLICEs
Net clk_c_enable_300: 12 loads, 12 LSLICEs
Net clk_c_enable_140: 3 loads, 3 LSLICEs
Net clk_c_enable_147: 3 loads, 3 LSLICEs
Net clk_c_enable_153: 3 loads, 3 LSLICEs
Net clk_c_enable_159: 3 loads, 3 LSLICEs
Net clk_c_enable_165: 3 loads, 3 LSLICEs
Net clk_c_enable_171: 3 loads, 3 LSLICEs
Net clk_c_enable_289: 1 loads, 1 LSLICEs
Net clk_c_enable_294: 2 loads, 2 LSLICEs
Net clk_c_enable_201: 1 loads, 1 LSLICEs
Net clk_c_enable_203: 1 loads, 1 LSLICEs
Net clk_c_enable_214: 1 loads, 1 LSLICEs
Net clk_c_enable_215: 1 loads, 1 LSLICEs
Net clk_c_enable_216: 1 loads, 1 LSLICEs
Net clk_c_enable_217: 1 loads, 1 LSLICEs
Net clk_c_enable_218: 1 loads, 1 LSLICEs
Net clk_c_enable_219: 1 loads, 1 LSLICEs
Net clk_c_enable_220: 1 loads, 1 LSLICEs
Net clk_c_enable_286: 1 loads, 1 LSLICEs
Net clk1_enable_74: 1 loads, 1 LSLICEs
Net clk_c_enable_266: 1 loads, 1 LSLICEs
Net clk1_enable_75: 1 loads, 1 LSLICEs
Net clk1_enable_76: 1 loads, 1 LSLICEs
Net clk_c_enable_290: 1 loads, 1 LSLICEs
Net clk_c_enable_285: 1 loads, 1 LSLICEs
Net clk_c_enable_288: 1 loads, 1 LSLICEs
Net clk_c_enable_281: 1 loads, 1 LSLICEs
Net clk_c_enable_284: 1 loads, 1 LSLICEs
Net clk_c_enable_287: 1 loads, 1 LSLICEs
Net clk_c_enable_292: 1 loads, 1 LSLICEs
Net clk1_enable_1: 1 loads, 1 LSLICEs
Net ikey_6: 1 loads, 1 LSLICEs
Net clk1_enable_88: 1 loads, 1 LSLICEs
Net clk1_enable_89: 1 loads, 1 LSLICEs
Net clk_c_enable_183: 1 loads, 1 LSLICEs
Net clk_N_905_enable_4: 2 loads, 2 LSLICEs
Net digiseg_rtc/clk_c_enable_275: 4 loads, 4 LSLICEs
Net digiseg_rtc/clk_c_enable_239: 13 loads, 13 LSLICEs
Net clk_c_enable_295: 2 loads, 2 LSLICEs
Net digiseg_rtc/clk_c_enable_263: 6 loads, 6 LSLICEs
Net digiseg_rtc/clk_c_enable_182: 1 loads, 1 LSLICEs
Net digiseg_rtc/clk_c_enable_185: 1 loads, 1 LSLICEs
Net digiseg_rtc/clk_c_enable_283: 2 loads, 2 LSLICEs
Net clk_c_enable_293: 2 loads, 2 LSLICEs
Net kb0/clk1_enable_4: 2 loads, 2 LSLICEs
Net kb0/count_1: 2 loads, 2 LSLICEs
Net kb0/row_3__N_1037: 4 loads, 4 LSLICEs
Net kb0/clk1_enable_7: 2 loads, 2 LSLICEs
Net kb0/clk1_enable_11: 2 loads, 2 LSLICEs
Net kb0/clk1_enable_15: 2 loads, 2 LSLICEs
Net eeprom_rtc_alarm0/clk_c_enable_51: 3 loads, 3 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_86: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_87: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_24: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_26: 2 loads, 2 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_37: 3 loads, 3 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_6: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_9: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_5: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk_c_enable_175: 2 loads, 2 LSLICEs
Net eeprom_rtc_alarm0/clk_c_enable_181: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_4: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_7: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_8: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_10: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_11: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_12: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_13: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_14: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_15: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_16: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_17: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_18: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_19: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_20: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_90: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_92: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_89: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_21: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_22: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_23: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk_c_enable_247: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_27: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_28: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_29: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_30: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_31: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_32: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_67: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_65: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_75: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_33: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_48: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_49: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_85: 3 loads, 3 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_64: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_73: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_57: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_74: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_56: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_77: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_42: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_43: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_44: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_72: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_59: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_47: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_79: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_51: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_45: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_46: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_50: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_52: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_53: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_54: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_55: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_58: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_60: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_61: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_62: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_63: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_66: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_68: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_69: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_70: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_71: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_76: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_78: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_80: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_81: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_82: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_83: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_84: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk_c_enable_282: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_88: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_91: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_93: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_94: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_95: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_96: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_97: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_98: 1 loads, 1 LSLICEs
Net eeprom_rtc_alarm0/clk1_enable_99: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_2: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_3: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_4: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_5: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_6: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_7: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_8: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_9: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_10: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_11: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_12: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_13: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_14: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_15: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_16: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_17: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_18: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_19: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_20: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_21: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_22: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_23: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_24: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_25: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_26: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_27: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_28: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_29: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_30: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_31: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_32: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_33: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_34: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_35: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_36: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_37: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_38: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_39: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_40: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_41: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_42: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_43: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_44: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_45: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_46: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_47: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_48: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_49: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_71: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_51: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_90: 2 loads, 2 LSLICEs
Net rtc0/clk1_enable_86: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_85: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_84: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_83: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_82: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_81: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_80: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_87: 6 loads, 6 LSLICEs
Net rtc0/clk1_enable_61: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_62: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_63: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_64: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_65: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_66: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_67: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_69: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_70: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_73: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_77: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_78: 1 loads, 1 LSLICEs
Net rtc0/clk1_enable_79: 1 loads, 1 LSLICEs
Number of LSRs: 38
Net n20035: 1 loads, 1 LSLICEs
Net n44781: 1 loads, 1 LSLICEs
Net n44780: 1 loads, 1 LSLICEs
Net n48655: 1 loads, 1 LSLICEs
Net n48648: 1 loads, 1 LSLICEs
Net n48748: 1 loads, 1 LSLICEs
Net n44700: 1 loads, 1 LSLICEs
Net page_update: 1 loads, 1 LSLICEs
Net n44554: 1 loads, 1 LSLICEs
Net n23717: 2 loads, 2 LSLICEs
Net n23524: 12 loads, 12 LSLICEs
Net n44956: 1 loads, 1 LSLICEs
Net rtc_clk/n15340: 13 loads, 13 LSLICEs
Net rtc_clk/n19990: 1 loads, 1 LSLICEs
Net n50623: 46 loads, 46 LSLICEs
Net n23558: 9 loads, 9 LSLICEs
Net n23523: 2 loads, 2 LSLICEs
Net clk_100hz/n15738: 13 loads, 13 LSLICEs
Net n45461: 2 loads, 2 LSLICEs
Net seg_blink_clk/n15282: 13 loads, 13 LSLICEs
Net seg_blink_clk/n19627: 1 loads, 1 LSLICEs
Net en_r: 28 loads, 28 LSLICEs
Net alarm_indicator_clk0/cnt1_23: 1 loads, 1 LSLICEs
Net alarm_indicator_clk0/n15741: 13 loads, 13 LSLICEs
Net kb_clk/n15658: 13 loads, 13 LSLICEs
Net kb_clk/n45564: 1 loads, 1 LSLICEs
Net digiseg_rtc/n23695: 2 loads, 2 LSLICEs
Net digiseg_rtc/n23730: 2 loads, 2 LSLICEs
Net digiseg_rtc/n24950: 4 loads, 4 LSLICEs
Net digiseg_rtc/n23692: 3 loads, 3 LSLICEs
Net digiseg_rtc/n23690: 4 loads, 4 LSLICEs
Net digiseg_rtc/n28549: 2 loads, 2 LSLICEs
Net n28552: 2 loads, 2 LSLICEs
Net kb0/n23535: 2 loads, 2 LSLICEs
Net eeprom_rtc_alarm0/n48972: 24 loads, 24 LSLICEs
Net eeprom_rtc_alarm0n48519: 13 loads, 13 LSLICEs
Net eeprom_rtc_alarm0cnt1_4: 1 loads, 1 LSLICEs
Net rtc0/n23720: 6 loads, 6 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net eeprom_rtc_alarm0/optlines_9: 183 loads
Net offset_0: 133 loads
Net eeprom_rtc_alarm0/n48791: 123 loads
Net eprom_rtc_dir: 121 loads
Net n48732: 117 loads
Net main_sm_2: 116 loads
Net main_sm_0: 112 loads
Net n50623: 98 loads
Net sub_state_1: 84 loads
Net sda_out: 81 loads

===========
UFM Summary.
===========
UFM Size: 767 Pages (128*767 Bits).
UFM Utilization: General Purpose Flash Memory.
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