用小脚丫FPGA的电赛训练平台完成DDS任意波形发生器/PC远程控制

内容介绍

1 项目需求:

DDS任意波形发生器/本地控制

通过板上的高速DAC（10bits/125Msps）配合FPGA内部DDS的逻辑，生成波形可调（正弦波、三角波、方波）、频率可调（DC-）、幅度可调的波形
生成模拟信号的频率范围为DC-20MHz，调节精度为1Hz
生成模拟信号的幅度为最大1Vpp，调节范围为0.1V-1V
在OLED上显示当前波形的形状、波形的频率以及幅度
利用板上旋转编码器和按键能够对波形进行切换、进行参数调节

2 完成的功能及达到的性能

可以生成三角波，正弦波，锯齿波和方波的波形。
频率可以到2MHZ
调节精度达到0.045，经过内部定义实际旋转拨码器可以达到精度1HZ
电压幅度1V峰峰值，可有四档幅度调制，最小0.1V
可以在OLED显示波形，频率和幅度
可以通过旋转编码器和6个按键进行调节频率，波形。同时在示波器和OLED上进行显示。

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3 实现思路

主要是DDS的原理，通过控制相位累加器达到控制波形频率的目的。频率由时钟，相位的位数，和频率控制字计算确定。为有完整的波形，一个周期至少有5-6个采样点。比如12M时钟可以生成2MHZ的波形，每周期有6个点。相位累加器的字宽和时钟频率决定最小精度。
电路板上带有一个10bit的120MADC,就生成1024个采样点的波表。通过ram_dp的IP核来生成RAM. 如果倍频可以产生120M和216M的时钟都可以获得更高的频率输出。
板载旋转编码器和6个按键方便控制。可控制频率控制字f_inc, vot电压因子，波形选择。
通过OLED12864的综合电路进行OLED屏幕的输出。

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4 实现过程

Encoder提供旋转编码器的功能。使用电子森林的例程。不必修改。

 Module: Encoder
// 
// Author: Step
// 
// Description: Driver for rotary encoder
// 
// Web: www.stepfapga.com
// 
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date:   |Changes Made:
// V1.0     |2016/04/20   |Initial ver
// --------------------------------------------------------------------
module Encoder
(
input					clk_in,			//系统时钟
input					rst_n_in,		//系统复位，低有效
input					key_a,			//旋转编码器A管脚
input					key_b,			//旋转编码器B管脚
input					key_ok,			//旋转编码器D管脚
output	reg				Left_pulse,		//左旋转脉冲输出
output	reg				Right_pulse,	//右旋转脉冲输出
output					OK_pulse		//按动脉冲输出
);

电压控制系数部分：

always @(posedge clk or negedge rst) begin
	if(!rst)
		cnt<=2'd0;
	else if(key_pulse) begin
		if(cnt==2'd3)
			cnt<=2'd0;
		else
			cnt<=cnt+2'd1;
	end
end

always @(*) begin
	case(cnt)
		2'd0: vot<=4'd1;
		2'd1: vot<=4'd2;
		2'd2: vot<=4'd5;
		2'd3: vot<=4'd10;
		default:vot<=4'd1;
	endcase

波形选择部分，例化了按键消抖的功能：

always @(posedge clk or negedge rst) begin
	if(!rst)
		cnt<=2'd0;
	else if(key_pulse) begin
		if(cnt==2'd3)
			cnt<=2'd0;
		else
			cnt<=cnt+2'd1;
	end
end

always @(*) begin
	case(cnt)
		2'd0: vot<=4'd1;
		2'd1: vot<=4'd2;
		2'd2: vot<=4'd5;
		2'd3: vot<=4'd10;
		default:vot<=4'd1;
	endcase

频率控制字是计算好要的频率，把频率控制字写进去的。

module f_inc_gen(
	input clk,
	input rst_n,
	input key_a,
	input key_b,
	input key_ok,
	
	output reg	[27:0] f_inc

);

wire Left_pulse;
wire Right_pulse;
wire OK_pulse;

Encoder u_Encoder(
	.clk_in			(clk		),
	.rst_n_in		(rst_n		),
	.key_a			(key_a		),
	.key_b			(key_b		),
	.key_ok			(key_ok		),
	.Left_pulse		(Left_pulse	),
	.Right_pulse	(Right_pulse),
	.OK_pulse		(OK_pulse	)


);

reg [3:0] cnt;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt<=4'd0;
	end
	else if (OK_pulse) begin
		if(cnt==4'd10) begin
			cnt<=4'd0;
		end
		else cnt<=cnt+4'd1;
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		f_inc<=28'd0;
	else if(OK_pulse) begin
		case(cnt)
			4'd0:	f_inc=28'd23;
			4'd1:	f_inc=28'd4474;
			4'd2:	f_inc=28'd13422;
			4'd3:	f_inc=28'd22370;
			4'd4:	f_inc=28'd134218;
			4'd5:	f_inc=28'd223696;
			4'd6:	f_inc=28'd1342177;
			4'd7:	f_inc=28'd2236962;
			4'd8:	f_inc=28'd13421773;
			4'd9:	f_inc=28'd22369621;
			4'd10:	f_inc=28'd44739243;
			default: f_inc=28'd23;
		endcase
	end
	
	else if(Left_pulse) begin
		if(f_inc<=0)
			f_inc<=f_inc;
		else
			f_inc<=f_inc-28'd23;
	end
	
	else if(Right_pulse) begin
		if(f_inc>=28'd44739244)
			f_inc<=f_inc;
		else
			f_inc<=f_inc+28'd23;
	end
	else
		f_inc<=f_inc;
end

endmodule

DDS部分例化了，波形选择，电压系数，频率控制字的电路。声明了28位的相位累加器。例化了ram_dp做查找表。查找表内有1024个计算好的波形采样点。

f_inc_gen u_f_inc_gen(
	.clk				(clk		),
	.rst_n				(rst_n		),
	.key_a				(key_a		),
	.key_b				(key_b		),
	.key_ok				(key_ok		),
	.f_inc				(f_inc		)
);



wave_sel u_wave_sel( 
	.clk				(clk		),
	.rst				(rst_n		),
	.key_d				(key_d		),
	.key_e				(key_e		),
	.key_f				(key_f		),
	.key_g				(key_g		),
	.wave				(wave		)
);

wire [9:0] dac_dat_r;

ram_dp u_ram_dp(
	.Reset			(~rst_n		),
	.WE				(1'b0		),
	.WrClock		(1'b0		),
	.WrClockEn		(1'b0		),
	.WrAddress		(10'b0		),
	.Data			(10'b0		),
	.RdClock		(dac_clk	),
	.RdClockEn		(1'b1		),
	.RdAddress		(phase[27:18]),
	.Q				(dac_dat_r	)
);

oled12864模块得到从DDS来的wave，和电压类型，又有按键控制判断频率的显示数值。最后输出。

MAIN:begin
						if(cnt_main >= 5'd20) cnt_main <= 5'd6;
						else cnt_main <= cnt_main + 1'b1;
						case(cnt_main)	//MAIN状态
							5'd0:	begin state <= INIT; end
							5'd1:	begin y_p <= 8'hb0; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "------DDS-------";state <= SCAN; end
							5'd2:	begin y_p <= 8'hb1; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "Wave:           ";state <= SCAN; end
							5'd3:	begin y_p <= 8'hb2; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "Freq:         HZ";state <= SCAN; end
							5'd4:	begin y_p <= 8'hb3; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "Vot:    V       ";state <= SCAN; end																			
						    5'd5:	begin y_p <= 8'hb1; x_ph <= 8'h14; x_pl <= 8'h00; num <= 5'd4; char <= "Sine";state <= SCAN; end
							5'd6:	begin if(wave==2'b00)begin y_p <= 8'hb1; x_ph <= 8'h13; x_pl <= 8'h00; num <= 5'd8; char <= "Sine    ";state <= SCAN; end end
							5'd7:	begin if(wave==2'b01)begin y_p <= 8'hb1; x_ph <= 8'h13; x_pl <= 8'h00; num <= 5'd8; char <= "Sawtooth";state <= SCAN; end end
							5'd8:	begin if(wave==2'b10)begin y_p <= 8'hb1; x_ph <= 8'h13; x_pl <= 8'h00; num <= 5'd8; char <= "Triangle";state <= SCAN; end end
							5'd9:	begin if(wave==2'b11)begin y_p <= 8'hb1; x_ph <= 8'h13; x_pl <= 8'h00; num <= 5'd8; char <= "Square  ";state <= SCAN; end end
														
							//5'd10:	begin y_p <= 8'hb2; x_ph <= 8'h12; x_pl <= 8'h08; num <= 5'd 1; char <= data[47:44]; state <= SCAN; end
							//5'd11:	begin y_p <= 8'hb2; x_ph <= 8'h13; x_pl <= 8'h00; num <= 5'd 1; char <= data[43:40]; state <= SCAN; end
							5'd10:	begin y_p <= 8'hb2; x_ph <= 8'h13; x_pl <= 8'h08; num <= 5'd 1; char <= p1; state <= SCAN; end
							5'd11:	begin y_p <= 8'hb2; x_ph <= 8'h14; x_pl <= 8'h00; num <= 5'd 1; char <= p2; state <= SCAN; end
							5'd12:	begin y_p <= 8'hb2; x_ph <= 8'h14; x_pl <= 8'h08; num <= 5'd 1; char <= p3; state <= SCAN; end
							5'd13:	begin y_p <= 8'hb2; x_ph <= 8'h15; x_pl <= 8'h00; num <= 5'd 1; char <= p4; state <= SCAN; end
							5'd14:	begin y_p <= 8'hb2; x_ph <= 8'h15; x_pl <= 8'h08; num <= 5'd 1; char <= p5; state <= SCAN; end
							5'd15:	begin y_p <= 8'hb2; x_ph <= 8'h16; x_pl <= 8'h00; num <= 5'd 1; char <= p6; state <= SCAN; end
							5'd16:	begin y_p <= 8'hb2; x_ph <= 8'h16; x_pl <= 8'h08; num <= 5'd 1; char <= p7; state <= SCAN; end
							//5'd19:	begin y_p <= 8'hb2; x_ph <= 8'h16; x_pl <= 8'h00; num <= 5'd 1; char <= data[11:8]; state <= SCAN; end
							//5'd20:	begin y_p <= 8'hb2; x_ph <= 8'h16; x_pl <= 8'h08; num <= 5'd 1; char <= data[11:4]; state <= SCAN; end
								
							5'd17:	begin if(vot==4'd1)begin y_p <= 8'hb3; x_ph <= 8'h12; x_pl <= 8'h00; num <= 5'd4; char <= "1.00";state <= SCAN; end end
							5'd18:	begin if(vot==4'd2)begin y_p <= 8'hb3; x_ph <= 8'h12; x_pl <= 8'h00; num <= 5'd4; char <= "0.50";state <= SCAN; end end
							5'd19:	begin if(vot==4'd5)begin y_p <= 8'hb3; x_ph <= 8'h12; x_pl <= 8'h00; num <= 5'd4; char <= "0.20";state <= SCAN; end end
							5'd20:	begin if(vot==4'd10)begin y_p <= 8'hb3; x_ph <= 8'h12; x_pl <= 8'h00; num <= 5'd4; char <= "0.10";state <= SCAN; end end
							default: state <= IDLE;
						endcase
					end

Design Information

Command line:   map -a MachXO2 -p LCMXO2-4000HC -t CSBGA132 -s 4 -oc Commercial
     hanjia_4h_impl1.ngd -o hanjia_4h_impl1_map.ncd -pr hanjia_4h_impl1.prf -mp
     hanjia_4h_impl1.mrp -lpf
     C:/Mike_own/mike_fpga/ya_fpga/hanjia_4h/impl1/hanjia_4h_impl1.lpf -lpf
     C:/Mike_own/mike_fpga/ya_fpga/hanjia_4h/hanjia_4h.lpf -c 0 -gui -msgset
     C:/Mike_own/mike_fpga/ya_fpga/hanjia_4h/promote.xml 
Target Vendor:  LATTICE
Target Device:  LCMXO2-4000HCCSBGA132
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
Mapped on:  02/27/22  15:09:22


Design Summary
   Number of registers:    440 out of  4635 (9%)
      PFU registers:          440 out of  4320 (10%)
      PIO registers:            0 out of   315 (0%)
   Number of SLICEs:      1168 out of  2160 (54%)
      SLICEs as Logic/ROM:   1168 out of  2160 (54%)
      SLICEs as RAM:            0 out of  1620 (0%)
      SLICEs as Carry:        237 out of  2160 (11%)
   Number of LUT4s:        2333 out of  4320 (54%)
      Number used as logic LUTs:        1859
      Number used as distributed RAM:     0
      Number used as ripple logic:      474
      Number used as shift registers:     0
   Number of PIO sites used: 27 + 4(JTAG) out of 105 (30%)
   Number of block RAMs:  2 out of 10 (20%)
   Number of GSRs:        1 out of 1 (100%)
   EFB used :        No
   JTAG used :       No
   Readback used :   No
   Oscillator used : No
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  1 out of 2 (50%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  1
     Net clk_c: 288 loads, 288 rising, 0 falling (Driver: PIO clk )
   Number of Clock Enables:  74

     Net clk_c_enable_215: 7 loads, 7 LSLICEs
     Net u_OLED12832/clk_c_enable_34: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_30: 4 loads, 4 LSLICEs
     Net u_OLED12832/clk_c_enable_27: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_151: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_159: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_223: 9 loads, 9 LSLICEs
     Net u_OLED12832/clk_c_enable_43: 2 loads, 2 LSLICEs
     Net u_OLED12832/clk_c_enable_41: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_10: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_107: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_122: 4 loads, 4 LSLICEs
     Net u_OLED12832/clk_c_enable_178: 4 loads, 4 LSLICEs
     Net u_OLED12832/clk_c_enable_33: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_217: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_221: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_195: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_198: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_142: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_58: 2 loads, 2 LSLICEs
     Net u_OLED12832/clk_c_enable_42: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_53: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_57: 2 loads, 2 LSLICEs
     Net u_OLED12832/clk_c_enable_51: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_48: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_99: 10 loads, 10 LSLICEs
     Net u_OLED12832/clk_c_enable_100: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_55: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_96: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_101: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_102: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_103: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_105: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_117: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_109: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_110: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_111: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_112: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_130: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_115: 2 loads, 2 LSLICEs
     Net u_OLED12832/clk_c_enable_129: 2 loads, 2 LSLICEs
     Net u_OLED12832/clk_c_enable_116: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_118: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_119: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_125: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_120: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_124: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_128: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_196: 9 loads, 9 LSLICEs
     Net u_OLED12832/clk_c_enable_216: 2 loads, 2 LSLICEs
     Net u_OLED12832/clk_c_enable_126: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_199: 4 loads, 4 LSLICEs
     Net u_OLED12832/clk_c_enable_197: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_220: 3 loads, 3 LSLICEs
     Net u_OLED12832/clk_c_enable_200: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_210: 1 loads, 1 LSLICEs

     Net u_OLED12832/clk_c_enable_211: 1 loads, 1 LSLICEs
     Net u_OLED12832/clk_c_enable_213: 1 loads, 1 LSLICEs
     Net u_OLED12832/u_Encoder/cnt_20ms_5__N_322: 5 loads, 5 LSLICEs
     Net u_OLED12832/u_Encoder/clk_c_enable_23: 1 loads, 1 LSLICEs
     Net u_OLED12832/u_Encoder/Left_pulse_N_323: 1 loads, 1 LSLICEs
     Net u_DDS/u_wave_sel/clk_c_enable_12: 1 loads, 1 LSLICEs
     Net u_DDS/u_wave_sel/clk_c_enable_95: 1 loads, 1 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_g/clk_c_enable_186: 1 loads, 1 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_f/clk_c_enable_167: 1 loads, 1 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_e/clk_c_enable_166: 1 loads, 1 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_d/clk_c_enable_187: 1 loads, 1 LSLICEs
     Net u_DDS/u_v_factor/clk_c_enable_174: 3 loads, 3 LSLICEs
     Net u_DDS/u_v_factor/u_debounce/clk_c_enable_165: 1 loads, 1 LSLICEs
     Net u_DDS/u_f_inc_gen/clk_c_enable_202: 14 loads, 14 LSLICEs
     Net u_DDS/u_f_inc_gen/clk_c_enable_190: 6 loads, 6 LSLICEs
     Net u_DDS/u_f_inc_gen/u_Encoder/clk_c_enable_21: 1 loads, 1 LSLICEs
     Net u_DDS/u_f_inc_gen/u_Encoder/cnt_20ms_5__N_322: 5 loads, 5 LSLICEs
     Net u_DDS/u_f_inc_gen/u_Encoder/Left_pulse_N_323: 1 loads, 1 LSLICEs
   Number of LSRs:  33
     Net rst_n_c: 4 loads, 0 LSLICEs
     Net clk_c_enable_215: 1 loads, 1 LSLICEs
     Net u_OLED12832/n22957: 9 loads, 9 LSLICEs
     Net u_OLED12832/n22922: 3 loads, 3 LSLICEs
     Net u_OLED12832/n22884: 2 loads, 2 LSLICEs
     Net u_OLED12832/n28291: 2 loads, 2 LSLICEs
     Net u_OLED12832/n35813: 1 loads, 1 LSLICEs
     Net u_OLED12832/n22937: 2 loads, 2 LSLICEs
     Net u_OLED12832/n22926: 2 loads, 2 LSLICEs
     Net u_OLED12832/n22916: 1 loads, 1 LSLICEs
     Net u_OLED12832/n22912: 1 loads, 1 LSLICEs
     Net u_OLED12832/n22905: 2 loads, 2 LSLICEs
     Net u_OLED12832/n22895: 9 loads, 9 LSLICEs
     Net u_OLED12832/n25032: 2 loads, 2 LSLICEs
     Net u_OLED12832/n22888: 2 loads, 2 LSLICEs
     Net u_OLED12832/n22919: 1 loads, 1 LSLICEs
     Net u_OLED12832/n22987: 3 loads, 3 LSLICEs
     Net u_OLED12832/n22914: 1 loads, 1 LSLICEs
     Net u_OLED12832/n22999: 2 loads, 2 LSLICEs
     Net u_OLED12832/n22973: 5 loads, 5 LSLICEs
     Net u_OLED12832/u_Encoder/cnt_12__N_315: 7 loads, 7 LSLICEs
     Net u_OLED12832/u_Encoder/clk_c_enable_23: 3 loads, 3 LSLICEs
     Net u_DDS/u_wave_sel/n6: 1 loads, 1 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_g/key_edge_0: 10 loads, 10 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_f/key_edge_0: 10 loads, 10 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_e/key_edge_0: 10 loads, 10 LSLICEs
     Net u_DDS/u_wave_sel/u_debounce_d/key_edge_0: 10 loads, 10 LSLICEs
     Net u_DDS/u_v_factor/n23004: 2 loads, 2 LSLICEs
     Net u_DDS/u_v_factor/u_debounce/key_edge_0: 10 loads, 10 LSLICEs
     Net u_DDS/u_f_inc_gen/n4046: 1 loads, 1 LSLICEs
     Net u_DDS/u_f_inc_gen/n22991: 5 loads, 5 LSLICEs
     Net u_DDS/u_f_inc_gen/u_Encoder/cnt_12__N_315: 7 loads, 7 LSLICEs
     Net u_DDS/u_f_inc_gen/u_Encoder/clk_c_enable_21: 3 loads, 3 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net n40661: 270 loads
     Net n40662: 270 loads

     Net n3261: 269 loads
     Net n40663: 268 loads
     Net vot_3: 152 loads
     Net n3260: 140 loads
     Net cnt_main_0: 97 loads
     Net u_DDS/n40720: 88 loads
     Net u_OLED12832/cnt_main_3: 86 loads
     Net cnt_main_1: 83 loads




   Number of warnings:  0
   Number of errors:    0

项目的资源占用截图：

FuJ_xQbLUj6yTIjtrJIbbsq-vEQX

5遇到的主要难题

DDS的知识比较丰富。我尝试备频到120M输出20M波形。遇到了时序的问题。没有经验。经过排除法排查，是我写了个处理84位二进制数的bin2bcd模块用时太多造成的。还不会解决。要继续学习。感谢硬禾学堂提供的平台。