1 项目需求:利用ADC制作一个数字电压表

• 旋转电位计可以产生0-3.3V的电压
• 利用板上的串行ADC对电压进行转换
• 将电压值在板上的OLED屏幕上显示出来

2 完成的功能及达到的性能

• 可以通过OLED屏幕显示固定的信息：硬禾学堂，Vot Meter, Hanjia 2022字样。用FPGA12864的电路接口功能，学会了刷新和显示文字的控制方法。
• 能把电压值实时显示在屏幕上。旋转电位计，模拟电压发生变化，FPGA和高速比较器搭建的ADC对模拟量采样转化成8位的数字量。
• 对数字量使用FPGA综合的电路BIN2BCD,将2进制数值转化成BCD码。每4位BCD码对应一位十进制数值。通过内部综合的电路连接的方式将BCD码数据传进FPGA12864模块并进行实时显示。学习了二进制转十进制的方法。

3 实现思路

• 板载高速比较器，通过FPGA综合的电路功能可以实现ADC。
• 查看电路原理图可知，旋转电位计连接GPIO28.可知接入高速比较器AIN2,连到FPGA的12管脚。正好构成了ADC的电路连接。
• ADC转化的数字量为8位，通过bin2bcd转化成BCD码，再通过12864综合电路输出到OLED.

4 实现过程

• 在Lattice网站下载对应的ADC例程。主要有三个文件：adc_top,box_ave,sigmadelta_adc.对三个verlog程序进行综合就可以实现电路。
• 对adc_top.v文件进行修改。例化bin2bcd和oled12864电路。进行转化和数值输出。

wire [15:0]	bin_code = digital_out * 16'd129;
wire [19:0]	bcd_code;

bin_to_bcd u_bin_to_bcd
(
.rst_n				(rstn			),	
.bin_code			(bin_code		),	
.bcd_code			(bcd_code		)	

);

OLED12864 u_OLED12864
(.clk                (clk            ),		
.rst_n	            (rstn          ),	        	
.data		    (bcd_code[19:4]),	
.oled_clk           (oled_clk       ),
//.oled_csn           (oled_csn       ),
.oled_dat           (oled_dat       ),
.oled_dcn           (oled_dcn       ),
.oled_rst           (oled_rst       )
);

bin2bcd不用修改，直接使用电子森林的版本。

// Web: www.stepfpga.com
// 
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date:   |Changes Made:
// V1.0     |2016/04/20   |Initial ver
// --------------------------------------------------------------------
module bin_to_bcd
(
input						rst_n,	//系统复位，低有效
input		[15:0]			bin_code,	//需要进行BCD转码的二进制数据
output	reg	[19:0]			bcd_code	//转码后的BCD码型数据输出
);

oled12864，需要修改。主要是显示的内容和位置。

MAIN:begin
						if(cnt_main >= 5'd19) cnt_main <= 5'd17;//接下来执行空操作，实现数据只刷新一次
						else cnt_main <= cnt_main + 1'b1;
						case(cnt_main)	//MAIN状态							
							5'd0 :	begin state <= INIT; end
							
							5'd1 :	begin y_p <= 8'hb0; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16;  char <= "                ";state <= SCAN; end
							5'd2 :	begin y_p <= 8'hb1; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16;  char <= "                ";state <= SCAN; end												
							5'd3 :	begin y_p <= 8'hb2; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "                ";state <= SCAN; end
							5'd4 :	begin y_p <= 8'hb3; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "                ";state <= SCAN; end
							5'd5 :	begin y_p <= 8'hb4; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "                ";state <= SCAN; end
							5'd6 :	begin y_p <= 8'hb5; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "                ";state <= SCAN; end
							5'd7 :	begin y_p <= 8'hb6; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "                ";state <= SCAN; end
							5'd8 :	begin y_p <= 8'hb7; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "                ";state <= SCAN; end
							5'd9 :	begin y_p <= 8'hb0; x_ph <= 8'h12; x_pl <= 8'h00; mem_hanzi_num <= 8'd0; state <= CHINESE; end
							5'd10:	begin y_p <= 8'hb0; x_ph <= 8'h13; x_pl <= 8'h00; mem_hanzi_num <= 8'd2; state <= CHINESE; end
							5'd11 :	begin y_p <= 8'hb0; x_ph <= 8'h14; x_pl <= 8'h00; mem_hanzi_num <= 8'd4; state <= CHINESE; end
							5'd12:	begin y_p <= 8'hb0; x_ph <= 8'h15; x_pl <= 8'h00; mem_hanzi_num <= 8'd6; state <= CHINESE; end
							5'd13:	begin y_p <= 8'hb2; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "----------------";state <= SCAN; end
							5'd14:	begin y_p <= 8'hb3; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= " Vot Meter:     ";state <= SCAN; end
							5'd15:	begin y_p <= 8'hb5; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "       .  V     ";state <= SCAN; end
							5'd16:	begin y_p <= 8'hb7; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= "---HanJia--2022--";state <= SCAN; end
							5'd17:	begin y_p <= 8'hb5; x_ph <= 8'h13; x_pl <= 8'h00; num <= 5'd 1; char <= data[15:12]; state <= SCAN; end
							5'd18:	begin y_p <= 8'hb5; x_ph <= 8'h14; x_pl <= 8'h00; num <= 5'd 1; char <= data[11:8]; state <= SCAN; end
							5'd19:	begin y_p <= 8'hb5; x_ph <= 8'h14; x_pl <= 8'h10; num <= 5'd 1; char <= data[7:4]; state <= SCAN; end

最后综合的电路

使用的资源情况

Design Summary
   Number of slice registers: 316 out of  5280 (6%)
   Number of I/O registers:      1 out of   117 (1%)
   Number of LUT4s:           1143 out of  5280 (22%)
      Number of logic LUT4s:             987
      Number of inserted feedthru LUT4s:  38
      Number of replicated LUT4s:         28
      Number of ripple logic:             45 (90 LUT4s)
   Number of IO sites used:   17 out of 39 (44%)
      Number of IO sites used for general PIO: 17
      Number of IO sites used for I3C: 0 out of 2 (0%)
      (note: If I3C is not used, its site can be used as general PIO)
      Number of IO sites used for PIO+I3C: 17 out of 36 (47%)
      Number of IO sites used for OD+RGB IO buffers: 0 out of 3 (0%)
      (note: If RGB LED drivers are not used, sites can be used as OD outputs,
       see TN1288 iCE40 LED Driver Usage Guide)
      Number of IO sites used for PIO+I3C+OD+RGB: 17 out of 39 (44%)
   Number of DSPs:             1 out of 8 (12%)
   Number of I2Cs:             0 out of 2 (0%)
   Number of High Speed OSCs:  0 out of 1 (0%)
   Number of Low Speed OSCs:   0 out of 1 (0%)
   Number of RGB PWM:          0 out of 1 (0%)
   Number of RGB Drivers:      0 out of 1 (0%)
   Number of SCL FILTERs:      0 out of 2 (0%)
   Number of SRAMs:            0 out of 4 (0%)
   Number of WARMBOOTs:        0 out of 1 (0%)
   Number of SPIs:             0 out of 2 (0%)
   Number of EBRs:             6 out of 30 (20%)
   Number of PLLs:             0 out of 1 (0%)
   Number of Clocks:  1
      Net clk_c: 314 loads, 314 rising, 0 falling (Driver: Port clk_in)
   Number of Clock Enables:  28
      Net VCC_net: 18 loads, 0 SLICEs
      Net n15732: 14 loads, 14 SLICEs
      Net n15548: 1 loads, 1 SLICEs
      Net u_OLED12864.cnt_main_4__N_708: 6 loads, 6 SLICEs
      Net u_OLED12864.n15320: 5 loads, 5 SLICEs
      Net u_OLED12864.n15319: 7 loads, 7 SLICEs
      Net u_OLED12864.n15321: 5 loads, 5 SLICEs
      Net u_OLED12864.n15813: 2 loads, 2 SLICEs
      Net u_OLED12864.n15798: 2 loads, 2 SLICEs
      Net u_OLED12864.n15335: 16 loads, 16 SLICEs
      Net u_OLED12864.n15322: 5 loads, 5 SLICEs
      Net u_OLED12864.n14852: 1 loads, 1 SLICEs

      Net u_OLED12864.n15351: 8 loads, 8 SLICEs
      Net u_OLED12864.n15_c: 1 loads, 1 SLICEs
      Net u_OLED12864.n15350: 1 loads, 1 SLICEs
      Net u_OLED12864.n15352: 16 loads, 16 SLICEs
      Net u_OLED12864.n25: 1 loads, 1 SLICEs
      Net u_OLED12864.n15353: 7 loads, 7 SLICEs
      Net u_OLED12864.n15354: 5 loads, 5 SLICEs
      Net u_OLED12864.n15822: 2 loads, 2 SLICEs
      Net u_OLED12864.n30575: 1 loads, 1 SLICEs
      Net u_OLED12864.n15810: 2 loads, 2 SLICEs
      Net u_OLED12864.n30491: 2 loads, 2 SLICEs
      Net u_OLED12864.n15828: 6 loads, 6 SLICEs
      Net SSD_ADC.rollover: 8 loads, 8 SLICEs
      Net SSD_ADC.n16710: 10 loads, 10 SLICEs
      Net SSD_ADC.box_ave.latch_result: 8 loads, 8 SLICEs
      Net SSD_ADC.box_ave.accumulate: 6 loads, 6 SLICEs
   Number of LSRs:  2
      Net rst_n_N_415: 305 loads, 305 SLICEs
      Net u_OLED12864.n16723: 2 loads, 2 SLICEs
   Top 10 highest fanout non-clock nets:
      Net rst_n_N_415: 305 loads
      Net u_OLED12864.cnt_chinese[0]: 76 loads
      Net u_OLED12864.cnt_chinese[1]: 70 loads
      Net n15732: 68 loads
      Net u_OLED12864.mem_hanzi_num[2]: 57 loads
      Net u_OLED12864.mem_hanzi_num[1]: 56 loads
      Net u_OLED12864.cnt_main_4__N_705: 53 loads
      Net u_OLED12864.cnt_main[0]: 45 loads
      Net u_OLED12864.cnt_main[4]: 44 loads
      Net u_OLED12864.state[1]: 44 loads




   Number of warnings:  0
   Number of errors:    0

5 遇到的主要难题

初学FPGA, 软件使用并不熟悉。在电子森林里丰富的例程帮助下逐渐掌握。

看电路图分配管脚是个学习的过程。包括阅读Lattice sigmadelta ADC的历程说明以及怎样用在这块电路板上。都是学习提高的过程。回头再看觉得不难，但不知道的内容更多了。继续学习。