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2021暑假一起练-小脚丫FPGA电压表
使用小脚丫扩展板载数模转换芯片ADS7868读取电位器电压,通过spi接口OLED显示屏显示电压值
标签
FPGA
测试
darren185
更新2021-09-09
1109

1,项目要求：

  1. 旋转电位计可以产生0-3.3V的电压
  2. 利用板上的串行ADC对电压进行转换
  3. 将电压值在板上的OLED屏幕上显示出来

2,项目系统设计

项目需求分析：在本项目中，需要实现对adc芯片协议解析及逻辑编写，oled协议解析,数据转换,数据格式转换等内容。

由于板载资源丰富,包含流水灯,按键,拨码开关,数码管,温度传感器,adc采集,oled显示,为实现项目需求,同时尽可能多的使用板载资源,但由于第一次接触fpga,能力有限,本次项目中使用了led流水灯做系统运行指示灯,数码管显示ADC采集的数字量,通过ds18b20采集环境温度通过oled显示,同时通过oled屏显示转换后的电压值。

系统框图简图如下:

Ft4ZK8H9iIQcIiy79FGWCoHd8OZk

3,系统逻辑图

下图为fpga内部逻辑图,主要有6部分组成,adc_to_vol_uut功能为将adc采集到的数字量装换为0-33000(电压0-3.3V放大1000倍),bin_to_cbd_uut功能是将二进制数字转化为bcd码,方便oled显示,oled_12832_uut功能为oled驱动单元,显示电压及温度,ds18b2n_uut功能是温度采集驱动单元,ads7868_adc功能为模拟信号采集驱动单元,seg_led功能为数码管驱动单元FioWLnRF7SBoN0HBPNVN7t2pd6oP

下图是引脚分配及配置图:

FgWqFah0nyppcF9HAPdRUlfkUbHD

 

4、模块工程代码：

(1)ADS7868_ADC模块：此模块读取模拟通道电压值转换成数字量,该芯片转换精度为8位,即采集是数字量0-255。该模块包含:输入信号clk(为模块提供时钟信号),res_n(低电平复位信号),CS(adc芯片使能信号),adc_clk(adc芯片时钟信号),adc_dat(adc芯片数据输入输出引脚),adc_done(adc完成标志状态寄存器),adc_data(adc芯片读取电压值暂存寄存器),

系统时钟为12M,内部处理进行2分频,clk输出频率为6M,根据数据手册,从发送到读取数据加上起始位,总共34个clk,读取数据速率为:speed=6M/34=176K(bit/s),小于数据手册采样速率,符合逻辑,代码如下:

module ADS7868_ADC
(
input				clk,		//系统时钟
input				rst_n,  	//系统复位，低有效
output	reg			adc_cs,		//SPI总线CS
output	reg			adc_clk,	//SPI总线SCK
input				adc_dat,	//SPI总线SDA
output	reg			adc_done,	//ADC采样完成标志
output	reg [7:0]	 adc_data	//ADC采样数据
);	 
	 
	localparam HIGH	= 1'b1, LOW = 1'b0;	 
	 reg [7:0] cnt; //计数器
always @(posedge clk or negedge rst_n)
	if(!rst_n) cnt <= 1'b0;
	else if(cnt >= 8'd34) cnt <= 1'b0;
	else cnt <= cnt + 1'b1;
 
reg [7:0] data;
always @(posedge clk or negedge rst_n)
	if(!rst_n) begin
		adc_cs <= HIGH; adc_clk <= HIGH;
	end else case(cnt)
		8'd0 :  begin adc_cs <= HIGH; adc_clk <= HIGH; end
		8'd1 :  begin adc_cs <= LOW;  adc_clk <= HIGH; end
		8'd2,
		8'd4,
		8'd6,
		8'd8,
		8'd10,
		8'd12,
		8'd14,
		8'd16,
		8'd18,
		8'd20,
		8'd22,
		8'd24,
		8'd26,
		8'd28,
		8'd30,
		8'd32:	
				begin adc_cs <= LOW;  adc_clk <= LOW;  end
		8'd3 :  begin adc_cs <= LOW;  adc_clk <= HIGH; end //0
		8'd5 :  begin adc_cs <= LOW;  adc_clk <= HIGH; end //1
		8'd7 :  begin adc_cs <= LOW;  adc_clk <= HIGH; end //2
		8'd9 :  begin adc_cs <= LOW;  adc_clk <= HIGH; data[7] <= adc_dat; end //3
		8'd11 : begin adc_cs <= LOW;  adc_clk <= HIGH; data[6] <= adc_dat; end //4
		8'd13 : begin adc_cs <= LOW;  adc_clk <= HIGH; data[5] <= adc_dat; end //5
		8'd15 : begin adc_cs <= LOW;  adc_clk <= HIGH; data[4] <= adc_dat; end //6
		8'd17 : begin adc_cs <= LOW;  adc_clk <= HIGH; data[3] <= adc_dat; end //7
		8'd19 : begin adc_cs <= LOW;  adc_clk <= HIGH; data[2] <= adc_dat; end //8
		8'd21 : begin adc_cs <= LOW;  adc_clk <= HIGH; data[1] <= adc_dat; end //9
		8'd23 : begin adc_cs <= LOW;  adc_clk <= HIGH; data[0] <= adc_dat; end //10
		8'd25 : begin adc_cs <= LOW;  adc_clk <= HIGH; adc_data <= data; end //11
		8'd27 : begin adc_cs <= LOW;  adc_clk <= HIGH; adc_done <= HIGH; end //12
		8'd29 : begin adc_cs <= LOW;  adc_clk <= HIGH; adc_done <= LOW; end //13
		8'd31 : begin adc_cs <= LOW;  adc_clk <= HIGH; end //14
		8'd33 : begin adc_cs <= LOW;  adc_clk <= HIGH; end //15
		8'd34 : begin adc_cs <= HIGH;  adc_clk <= HIGH; end
		default : begin adc_cs <= HIGH;  adc_clk <= HIGH;  end
	endcase
	endmodule

(2)ADC数字量转换成电压值模块，该模块实现adc采集的数字量通过电压转换成0-3.3V电压,为了方便后续处理,将电压值放大1000倍,保留整数部分 。该模块包含:res_n(低电平复位信号), adc_code(adc数据输入),vol_code(adc转换后电压值暂存寄存器)代码如下:

module adc_to_vol
 
(
input						rst_n,			// system reset, active low
input		[7:0]	adc_code,		// binary code
output	reg	[15:0]	vol_code		// bcd code
);

  
always@(rst_n)begin      
	         
	if(!rst_n) vol_code <= 0;      
	else begin         
		 
	vol_code<=(adc_code*3300)/255;                           
		        
		   
	end  
end

endmodule

在OLED的显示模块，输入clk为时钟信号，rst为复位信号，sw为电压数据，t为温度数据，输出csn,rst,dcn,clk,dat 5个信号控制OLED的显示，在MAIN状态下显示，INIT为初始化状态，SCAN为刷屏状态，WRITE为写状态，将数据按照SPI时序发送给屏幕。在输入信号中设置了一个信号位display_flag,通过改变信号位来实现时间和温度数据停止显示，同时又没有使时间停止计数。

module OLED12832
(
	input				clk,		//12MHz系统时钟
	input				rst_n,		//系统复位，低有效

	input		[24:0]	sw,		//
	input [0:0]status,
	input [15:0] t,
	output	reg			oled_csn,	//OLCD液晶屏使能
	output	reg			oled_rst,	//OLCD液晶屏复位
	output	reg			oled_dcn,	//OLCD数据指令控制
	output	reg			oled_clk,	//OLCD时钟信号
	output	reg			oled_dat	//OLCD数据信号
);

	localparam INIT_DEPTH = 16'd25; //LCD初始化的命令的数量
	localparam IDLE = 6'h1, MAIN = 6'h2, INIT = 6'h4, SCAN = 6'h8, WRITE = 6'h10, DELAY = 6'h20;
	localparam HIGH	= 1'b1, LOW = 1'b0;
	localparam DATA	= 1'b1, CMD = 1'b0;

	reg [7:0] cmd [24:0];
	reg [39:0] mem [122:0];
	reg [15:0] dec [100:0];
	reg	[7:0]	y_p, x_ph, x_pl;
	reg	[(8*21-1):0] char;
	reg	[7:0]	num, char_reg;				//
	reg	[4:0]	cnt_main, cnt_init, cnt_scan, cnt_write;
	reg	[15:0]	num_delay, cnt_delay, cnt;
	reg	[5:0] 	state, state_back;
reg[3:0]qianwei;//千位

 reg[3:0]baiwei;//百位

 reg[3:0]shiwei;//十位

reg[3:0]gewei;//个位
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt_main <= 1'b0; cnt_init <= 1'b0; cnt_scan <= 1'b0; cnt_write <= 1'b0;
			y_p <= 1'b0; x_ph <= 1'b0; x_pl <= 1'b0;
			num <= 1'b0; char <= 1'b0; char_reg <= 1'b0;
			num_delay <= 16'd5; cnt_delay <= 1'b0; cnt <= 1'b0;
			oled_csn <= HIGH; oled_rst <= HIGH; oled_dcn <= CMD; oled_clk <= HIGH; oled_dat <= LOW;
			state <= IDLE; state_back <= IDLE;
		end else begin
			case(state)
				IDLE:begin
						cnt_main <= 1'b0; cnt_init <= 1'b0; cnt_scan <= 1'b0; cnt_write <= 1'b0;
						y_p <= 1'b0; x_ph <= 1'b0; x_pl <= 1'b0;
						num <= 1'b0; char <= 1'b0; char_reg <= 1'b0;
						num_delay <= 16'd5; cnt_delay <= 1'b0; cnt <= 1'b0;
						oled_csn <= HIGH; oled_rst <= HIGH; oled_dcn <= CMD; oled_clk <= HIGH; oled_dat <= LOW;
						state <= MAIN; state_back <= MAIN;
					end
				MAIN:begin
						if(cnt_main >= 5'd8) cnt_main <= 5'd5;
						else cnt_main <= cnt_main + 1'b1;
						if(status==1'b1)
							state<=IDLE;
						else
							begin
								case(cnt_main)	//MAIN状态
									5'd0:	begin state <= INIT; end
									5'd1:	begin y_p <= 8'hb0; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd15; char <= "TEMP           ";state <= SCAN; end
									5'd2:	begin y_p <= 8'hb1; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd15; char <= "---------------";state <= SCAN; end
									5'd3:	begin y_p <= 8'hb2; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd15; char <= "voltage        ";state <= SCAN; end
									5'd4:	begin y_p <= 8'hb3; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd15; char <= "---------------";state <= SCAN; end

									5'd5:	begin y_p <= 8'hb0; x_ph <= 8'h15; x_pl <= 8'h00; num <= 5'd 6; char <= {4'd0,sw[23:20],4'd0,sw[19:16],".",4'd0,sw[15:12],"  "}; state <= SCAN; end
									 5'd6:	begin y_p <= 8'hb1; x_ph <= 8'h15; x_pl <= 8'h00; num <= 5'd 6; char <= "------"; state <= SCAN; end
 
									5'd7:	begin y_p <= 8'hb2; x_ph <= 8'h15; x_pl <= 8'h00; num <= 5'd 6; char <= {4'd0,t[15:12],".",4'd0,t[11:8],4'd0,t[7:4],4'd0,t[3:0],"V"}; state <= SCAN; end
									  5'd8:	begin y_p <= 8'hb3; x_ph <= 8'h15; x_pl <= 8'h00; num <= 5'd 6; char <= "------"; state <= SCAN; end

									default: state <= IDLE;
								endcase
							end
					end
				INIT:begin	//初始化状态
						case(cnt_init)
							5'd0:	begin oled_rst <= LOW; cnt_init <= cnt_init + 1'b1; end	//复位有效
							5'd1:	begin num_delay <= 16'd25000; state <= DELAY; state_back <= INIT; cnt_init <= cnt_init + 1'b1; end	//延时大于3us
							5'd2:	begin oled_rst <= HIGH; cnt_init <= cnt_init + 1'b1; end	//复位恢复
							5'd3:	begin num_delay <= 16'd25000; state <= DELAY; state_back <= INIT; cnt_init <= cnt_init + 1'b1; end	//延时大于220us
							5'd4:	begin
										if(cnt>=INIT_DEPTH) begin	//当25条指令及数据发出后，配置完成
											cnt <= 1'b0;
											cnt_init <= cnt_init + 1'b1;
										end else begin
											cnt <= cnt + 1'b1; num_delay <= 16'd5;
											oled_dcn <= CMD; char_reg <= cmd[cnt]; state <= WRITE; state_back <= INIT;
										end
									end
							5'd5:	begin cnt_init <= 1'b0; state <= MAIN; end	//初始化完成，返回MAIN状态
							default: state <= IDLE;
						endcase
					end
				SCAN:begin	//刷屏状态，从RAM中读取数据刷屏
						if(cnt_scan == 5'd11) begin
							if(num) cnt_scan <= 5'd3;
							else cnt_scan <= cnt_scan + 1'b1;
						end else if(cnt_scan == 5'd12) cnt_scan <= 1'b0;
						else cnt_scan <= cnt_scan + 1'b1;
						case(cnt_scan)
							5'd 0:	begin oled_dcn <= CMD; char_reg <= y_p; state <= WRITE; state_back <= SCAN; end		//定位列页地址
							5'd 1:	begin oled_dcn <= CMD; char_reg <= x_pl; state <= WRITE; state_back <= SCAN; end	//定位行地址低位
							5'd 2:	begin oled_dcn <= CMD; char_reg <= x_ph; state <= WRITE; state_back <= SCAN; end	//定位行地址高位

							5'd 3:	begin num <= num - 1'b1;end
							5'd 4:	begin oled_dcn <= DATA; char_reg <= 8'h00; state <= WRITE; state_back <= SCAN; end	//将5*8点阵编程8*8
							5'd 5:	begin oled_dcn <= DATA; char_reg <= 8'h00; state <= WRITE; state_back <= SCAN; end	//将5*8点阵编程8*8
							5'd 6:	begin oled_dcn <= DATA; char_reg <= 8'h00; state <= WRITE; state_back <= SCAN; end	//将5*8点阵编程8*8
							5'd 7:	begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][39:32]; state <= WRITE; state_back <= SCAN; end
							5'd 8:	begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][31:24]; state <= WRITE; state_back <= SCAN; end
							5'd 9:	begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][23:16]; state <= WRITE; state_back <= SCAN; end
							5'd10:	begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][15: 8]; state <= WRITE; state_back <= SCAN; end
							5'd11:	begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][ 7: 0]; state <= WRITE; state_back <= SCAN; end
							5'd12:	begin state <= MAIN; end
							default: state <= IDLE;
						endcase
					end
				WRITE:begin	//WRITE状态，将数据按照SPI时序发送给屏幕
						if(cnt_write >= 5'd17) cnt_write <= 1'b0;
						else cnt_write <= cnt_write + 1'b1;
						case(cnt_write)
							5'd 0:	begin oled_csn <= LOW; end	//9位数据最高位为命令数据控制位
							5'd 1:	begin oled_clk <= LOW; oled_dat <= char_reg[7]; end	//先发高位数据
							5'd 2:	begin oled_clk <= HIGH; end
							5'd 3:	begin oled_clk <= LOW; oled_dat <= char_reg[6]; end
							5'd 4:	begin oled_clk <= HIGH; end
							5'd 5:	begin oled_clk <= LOW; oled_dat <= char_reg[5]; end
							5'd 6:	begin oled_clk <= HIGH; end
							5'd 7:	begin oled_clk <= LOW; oled_dat <= char_reg[4]; end
							5'd 8:	begin oled_clk <= HIGH; end
							5'd 9:	begin oled_clk <= LOW; oled_dat <= char_reg[3]; end
							5'd10:	begin oled_clk <= HIGH; end
							5'd11:	begin oled_clk <= LOW; oled_dat <= char_reg[2]; end
							5'd12:	begin oled_clk <= HIGH; end
							5'd13:	begin oled_clk <= LOW; oled_dat <= char_reg[1]; end
							5'd14:	begin oled_clk <= HIGH; end
							5'd15:	begin oled_clk <= LOW; oled_dat <= char_reg[0]; end	//后发低位数据
							5'd16:	begin oled_clk <= HIGH; end
							5'd17:	begin oled_csn <= HIGH; state <= DELAY; end	//
							default: state <= IDLE;
						endcase
					end
				DELAY:begin	//延时状态
						if(cnt_delay >= num_delay) begin
							cnt_delay <= 16'd0; state <= state_back;
						end else cnt_delay <= cnt_delay + 1'b1;
					end
				default:state <= IDLE;
			endcase
		end
	end

	//OLED配置指令数据
	always@(posedge rst_n)
		begin
			cmd[ 0] = {8'hae};
			cmd[ 1] = {8'h00};
			cmd[ 2] = {8'h10};
			cmd[ 3] = {8'h00};
			cmd[ 4] = {8'hb0};
			cmd[ 5] = {8'h81};
			cmd[ 6] = {8'hff};
			cmd[ 7] = {8'ha1};
			cmd[ 8] = {8'ha6};
			cmd[ 9] = {8'ha8};
			cmd[10] = {8'h1f};
			cmd[11] = {8'hc8};
			cmd[12] = {8'hd3};
			cmd[13] = {8'h00};
			cmd[14] = {8'hd5};
			cmd[15] = {8'h80};
			cmd[16] = {8'hd9};
			cmd[17] = {8'h1f};
			cmd[18] = {8'hda};
			cmd[19] = {8'h00};
			cmd[20] = {8'hdb};
			cmd[21] = {8'h40};
			cmd[22] = {8'h8d};
			cmd[23] = {8'h14};
			cmd[24] = {8'haf};
		end

	//5*8点阵字库数据
	always@(posedge rst_n)
		begin
			mem[  0] = {8'h3E, 8'h51, 8'h49, 8'h45, 8'h3E};   // 48  0
			mem[  1] = {8'h00, 8'h42, 8'h7F, 8'h40, 8'h00};   // 49  1
			mem[  2] = {8'h42, 8'h61, 8'h51, 8'h49, 8'h46};   // 50  2
			mem[  3] = {8'h21, 8'h41, 8'h45, 8'h4B, 8'h31};   // 51  3
			mem[  4] = {8'h18, 8'h14, 8'h12, 8'h7F, 8'h10};   // 52  4
			mem[  5] = {8'h27, 8'h45, 8'h45, 8'h45, 8'h39};   // 53  5
			mem[  6] = {8'h3C, 8'h4A, 8'h49, 8'h49, 8'h30};   // 54  6
			mem[  7] = {8'h01, 8'h71, 8'h09, 8'h05, 8'h03};   // 55  7
			mem[  8] = {8'h36, 8'h49, 8'h49, 8'h49, 8'h36};   // 56  8
			mem[  9] = {8'h06, 8'h49, 8'h49, 8'h29, 8'h1E};   // 57  9
			mem[ 10] = {8'h7C, 8'h12, 8'h11, 8'h12, 8'h7C};   // 65  A
			mem[ 11] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h36};   // 66  B
			mem[ 12] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h22};   // 67  C
			mem[ 13] = {8'h7F, 8'h41, 8'h41, 8'h22, 8'h1C};   // 68  D
			mem[ 14] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h41};   // 69  E
			mem[ 15] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h01};   // 70  F

			mem[ 32] = {8'h00, 8'h00, 8'h00, 8'h00, 8'h00};   // 32  sp
			mem[ 33] = {8'h00, 8'h00, 8'h2f, 8'h00, 8'h00};   // 33  !
			mem[ 34] = {8'h00, 8'h07, 8'h00, 8'h07, 8'h00};   // 34
			mem[ 35] = {8'h14, 8'h7f, 8'h14, 8'h7f, 8'h14};   // 35  #
			mem[ 36] = {8'h24, 8'h2a, 8'h7f, 8'h2a, 8'h12};   // 36  $
			mem[ 37] = {8'h62, 8'h64, 8'h08, 8'h13, 8'h23};   // 37  %
			mem[ 38] = {8'h36, 8'h49, 8'h55, 8'h22, 8'h50};   // 38  &
			mem[ 39] = {8'h00, 8'h05, 8'h03, 8'h00, 8'h00};   // 39  '
			mem[ 40] = {8'h00, 8'h1c, 8'h22, 8'h41, 8'h00};   // 40  (
			mem[ 41] = {8'h00, 8'h41, 8'h22, 8'h1c, 8'h00};   // 41  )
			mem[ 42] = {8'h14, 8'h08, 8'h3E, 8'h08, 8'h14};   // 42  *
			mem[ 43] = {8'h08, 8'h08, 8'h3E, 8'h08, 8'h08};   // 43  +
			mem[ 44] = {8'h00, 8'h00, 8'hA0, 8'h60, 8'h00};   // 44  ,
			mem[ 45] = {8'h08, 8'h08, 8'h08, 8'h08, 8'h08};   // 45  -
			mem[ 46] = {8'h00, 8'h60, 8'h60, 8'h00, 8'h00};   // 46  .
			mem[ 47] = {8'h20, 8'h10, 8'h08, 8'h04, 8'h02};   // 47  /
			mem[ 48] = {8'h3E, 8'h51, 8'h49, 8'h45, 8'h3E};   // 48  0
			mem[ 49] = {8'h00, 8'h42, 8'h7F, 8'h40, 8'h00};   // 49  1
			mem[ 50] = {8'h42, 8'h61, 8'h51, 8'h49, 8'h46};   // 50  2
			mem[ 51] = {8'h21, 8'h41, 8'h45, 8'h4B, 8'h31};   // 51  3
			mem[ 52] = {8'h18, 8'h14, 8'h12, 8'h7F, 8'h10};   // 52  4
			mem[ 53] = {8'h27, 8'h45, 8'h45, 8'h45, 8'h39};   // 53  5
			mem[ 54] = {8'h3C, 8'h4A, 8'h49, 8'h49, 8'h30};   // 54  6
			mem[ 55] = {8'h01, 8'h71, 8'h09, 8'h05, 8'h03};   // 55  7
			mem[ 56] = {8'h36, 8'h49, 8'h49, 8'h49, 8'h36};   // 56  8
			mem[ 57] = {8'h06, 8'h49, 8'h49, 8'h29, 8'h1E};   // 57  9
			mem[ 58] = {8'h00, 8'h36, 8'h36, 8'h00, 8'h00};   // 58  :
			mem[ 59] = {8'h00, 8'h56, 8'h36, 8'h00, 8'h00};   // 59  ;
			mem[ 60] = {8'h08, 8'h14, 8'h22, 8'h41, 8'h00};   // 60  <
			mem[ 61] = {8'h14, 8'h14, 8'h14, 8'h14, 8'h14};   // 61  =
			mem[ 62] = {8'h00, 8'h41, 8'h22, 8'h14, 8'h08};   // 62  >
			mem[ 63] = {8'h02, 8'h01, 8'h51, 8'h09, 8'h06};   // 63  ?
			mem[ 64] = {8'h32, 8'h49, 8'h59, 8'h51, 8'h3E};   // 64  @
			mem[ 65] = {8'h7C, 8'h12, 8'h11, 8'h12, 8'h7C};   // 65  A
			mem[ 66] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h36};   // 66  B
			mem[ 67] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h22};   // 67  C
			mem[ 68] = {8'h7F, 8'h41, 8'h41, 8'h22, 8'h1C};   // 68  D
			mem[ 69] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h41};   // 69  E
			mem[ 70] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h01};   // 70  F
			mem[ 71] = {8'h3E, 8'h41, 8'h49, 8'h49, 8'h7A};   // 71  G
			mem[ 72] = {8'h7F, 8'h08, 8'h08, 8'h08, 8'h7F};   // 72  H
			mem[ 73] = {8'h00, 8'h41, 8'h7F, 8'h41, 8'h00};   // 73  I
			mem[ 74] = {8'h20, 8'h40, 8'h41, 8'h3F, 8'h01};   // 74  J
			mem[ 75] = {8'h7F, 8'h08, 8'h14, 8'h22, 8'h41};   // 75  K
			mem[ 76] = {8'h7F, 8'h40, 8'h40, 8'h40, 8'h40};   // 76  L
			mem[ 77] = {8'h7F, 8'h02, 8'h0C, 8'h02, 8'h7F};   // 77  M
			mem[ 78] = {8'h7F, 8'h04, 8'h08, 8'h10, 8'h7F};   // 78  N
			mem[ 79] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h3E};   // 79  O
			mem[ 80] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h06};   // 80  P
			mem[ 81] = {8'h3E, 8'h41, 8'h51, 8'h21, 8'h5E};   // 81  Q
			mem[ 82] = {8'h7F, 8'h09, 8'h19, 8'h29, 8'h46};   // 82  R
			mem[ 83] = {8'h46, 8'h49, 8'h49, 8'h49, 8'h31};   // 83  S
			mem[ 84] = {8'h01, 8'h01, 8'h7F, 8'h01, 8'h01};   // 84  T
			mem[ 85] = {8'h3F, 8'h40, 8'h40, 8'h40, 8'h3F};   // 85  U
			mem[ 86] = {8'h1F, 8'h20, 8'h40, 8'h20, 8'h1F};   // 86  V
			mem[ 87] = {8'h3F, 8'h40, 8'h38, 8'h40, 8'h3F};   // 87  W
			mem[ 88] = {8'h63, 8'h14, 8'h08, 8'h14, 8'h63};   // 88  X
			mem[ 89] = {8'h07, 8'h08, 8'h70, 8'h08, 8'h07};   // 89  Y
			mem[ 90] = {8'h61, 8'h51, 8'h49, 8'h45, 8'h43};   // 90  Z
			mem[ 91] = {8'h00, 8'h7F, 8'h41, 8'h41, 8'h00};   // 91  [
			mem[ 92] = {8'h55, 8'h2A, 8'h55, 8'h2A, 8'h55};   // 92  .
			mem[ 93] = {8'h00, 8'h41, 8'h41, 8'h7F, 8'h00};   // 93  ]
			mem[ 94] = {8'h04, 8'h02, 8'h01, 8'h02, 8'h04};   // 94  ^
			mem[ 95] = {8'h40, 8'h40, 8'h40, 8'h40, 8'h40};   // 95  _
			mem[ 96] = {8'h00, 8'h01, 8'h02, 8'h04, 8'h00};   // 96  '
			mem[ 97] = {8'h20, 8'h54, 8'h54, 8'h54, 8'h78};   // 97  a
			mem[ 98] = {8'h7F, 8'h48, 8'h44, 8'h44, 8'h38};   // 98  b
			mem[ 99] = {8'h38, 8'h44, 8'h44, 8'h44, 8'h20};   // 99  c
			mem[100] = {8'h38, 8'h44, 8'h44, 8'h48, 8'h7F};   // 100 d
			mem[101] = {8'h38, 8'h54, 8'h54, 8'h54, 8'h18};   // 101 e
			mem[102] = {8'h08, 8'h7E, 8'h09, 8'h01, 8'h02};   // 102 f
			mem[103] = {8'h18, 8'hA4, 8'hA4, 8'hA4, 8'h7C};   // 103 g
			mem[104] = {8'h7F, 8'h08, 8'h04, 8'h04, 8'h78};   // 104 h
			mem[105] = {8'h00, 8'h44, 8'h7D, 8'h40, 8'h00};   // 105 i
			mem[106] = {8'h40, 8'h80, 8'h84, 8'h7D, 8'h00};   // 106 j
			mem[107] = {8'h7F, 8'h10, 8'h28, 8'h44, 8'h00};   // 107 k
			mem[108] = {8'h00, 8'h41, 8'h7F, 8'h40, 8'h00};   // 108 l
			mem[109] = {8'h7C, 8'h04, 8'h18, 8'h04, 8'h78};   // 109 m
			mem[110] = {8'h7C, 8'h08, 8'h04, 8'h04, 8'h78};   // 110 n
			mem[111] = {8'h38, 8'h44, 8'h44, 8'h44, 8'h38};   // 111 o
			mem[112] = {8'hFC, 8'h24, 8'h24, 8'h24, 8'h18};   // 112 p
			mem[113] = {8'h18, 8'h24, 8'h24, 8'h18, 8'hFC};   // 113 q
			mem[114] = {8'h7C, 8'h08, 8'h04, 8'h04, 8'h08};   // 114 r
			mem[115] = {8'h48, 8'h54, 8'h54, 8'h54, 8'h20};   // 115 s
			mem[116] = {8'h04, 8'h3F, 8'h44, 8'h40, 8'h20};   // 116 t
			mem[117] = {8'h3C, 8'h40, 8'h40, 8'h20, 8'h7C};   // 117 u
			mem[118] = {8'h1C, 8'h20, 8'h40, 8'h20, 8'h1C};   // 118 v
			mem[119] = {8'h3C, 8'h40, 8'h30, 8'h40, 8'h3C};   // 119 w
			mem[120] = {8'h44, 8'h28, 8'h10, 8'h28, 8'h44};   // 120 x
			mem[121] = {8'h1C, 8'hA0, 8'hA0, 8'hA0, 8'h7C};   // 121 y
			mem[122] = {8'h44, 8'h64, 8'h54, 8'h4C, 8'h44};   // 122 z
		end
always @(posedge rst_n) begin
	dec[0]={8'd48,8'd48};
	dec[1]={8'd48,8'd49};
	dec[2]={8'd48,8'd50};
	dec[3]={8'd48,8'd51};
	dec[4]={8'd48,8'd52};
	dec[5]={8'd48,8'd53};
	dec[6]={8'd48,8'd54};
	dec[7]={8'd48,8'd55};
	dec[8]={8'd48,8'd56};
	dec[9]={8'd48,8'd57};
	dec[10]={8'd49,8'd48};
	dec[11]={8'd49,8'd49};
	dec[12]={8'd49,8'd50};
	dec[13]={8'd49,8'd51};
	dec[14]={8'd49,8'd52};
	dec[15]={8'd49,8'd53};
	dec[16]={8'd49,8'd54};
	dec[17]={8'd49,8'd55};
	dec[18]={8'd49,8'd56};
	dec[19]={8'd49,8'd57};

	dec[20]={8'd50,8'd48};
	dec[21]={8'd50,8'd49};
	dec[22]={8'd50,8'd50};
	dec[23]={8'd50,8'd51};
	dec[24]={8'd50,8'd52};
	dec[25]={8'd50,8'd53};
	dec[26]={8'd50,8'd54};
	dec[27]={8'd50,8'd55};
	dec[28]={8'd50,8'd56};
	dec[29]={8'd50,8'd57};

	dec[30]={8'd51,8'd48};
	dec[31]={8'd51,8'd49};
	dec[32]={8'd51,8'd50};
	dec[33]={8'd51,8'd51};
	dec[34]={8'd51,8'd52};
	dec[35]={8'd51,8'd53};
	dec[36]={8'd51,8'd54};
	dec[37]={8'd51,8'd55};
	dec[38]={8'd51,8'd56};
	dec[39]={8'd51,8'd57};

	dec[40]={8'd52,8'd48};
	dec[41]={8'd52,8'd49};
	dec[42]={8'd52,8'd50};
	dec[43]={8'd52,8'd51};
	dec[44]={8'd52,8'd52};
	dec[45]={8'd52,8'd53};
	dec[46]={8'd52,8'd54};
	dec[47]={8'd52,8'd55};
	dec[48]={8'd52,8'd56};
	dec[49]={8'd52,8'd57};

	dec[50]={8'd53,8'd48};
	dec[51]={8'd53,8'd49};
	dec[52]={8'd53,8'd50};
	dec[53]={8'd53,8'd51};
	dec[54]={8'd53,8'd52};
	dec[55]={8'd53,8'd53};
	dec[56]={8'd53,8'd54};
	dec[57]={8'd53,8'd55};
	dec[58]={8'd53,8'd56};
	dec[59]={8'd53,8'd57};

	dec[60]={8'd54,8'd48};
	dec[61]={8'd54,8'd49};
	dec[62]={8'd54,8'd50};
	dec[63]={8'd54,8'd51};
	dec[64]={8'd54,8'd52};
	dec[65]={8'd54,8'd53};
	dec[66]={8'd54,8'd54};
	dec[67]={8'd54,8'd55};
	dec[68]={8'd54,8'd56};
	dec[69]={8'd54,8'd57};

	dec[70]={8'd55,8'd48};
	dec[71]={8'd55,8'd49};
	dec[72]={8'd55,8'd50};
	dec[73]={8'd55,8'd51};
	dec[74]={8'd55,8'd52};
	dec[75]={8'd55,8'd53};
	dec[76]={8'd55,8'd54};
	dec[77]={8'd55,8'd55};
	dec[78]={8'd55,8'd56};
	dec[79]={8'd55,8'd57};

	dec[80]={8'd56,8'd48};
	dec[81]={8'd56,8'd49};
	dec[82]={8'd56,8'd50};
	dec[83]={8'd56,8'd51};
	dec[84]={8'd56,8'd52};
	dec[85]={8'd56,8'd53};
	dec[86]={8'd56,8'd54};
	dec[87]={8'd56,8'd55};
	dec[88]={8'd56,8'd56};
	dec[89]={8'd56,8'd57};

	dec[90]={8'd57,8'd48};
	dec[91]={8'd57,8'd49};
	dec[92]={8'd57,8'd50};
	dec[93]={8'd57,8'd51};
	dec[94]={8'd57,8'd52};
	dec[95]={8'd57,8'd53};
	dec[96]={8'd57,8'd54};
	dec[97]={8'd57,8'd55};
	dec[98]={8'd57,8'd56};
	dec[99]={8'd57,8'd57};
end


endmodule

（3）数码管控制模块，此模块通过调用bin_to_bcd模块把从ADC模块上输出的数据转换为bcd码形式,该模块包含:  seg_data(输入要显示的数据),  input seg_dot(小数点显示标志位), output seg_sel(数码管片选引脚),output reg [7:0] (数码管驱动引脚) ,代码如下

module Seg_led
(
input 		[3:0]	seg_data,	//seg_data input
input				seg_dot,	//segment dot control
output				seg_sel,	//segment com port
output reg	[7:0]	seg_led		//MSB~LSB = DP,G,F,E,D,C,B,A
);

always@(seg_data)
	case(seg_data)
		4'h0: seg_led = {seg_dot,7'h3f};  //  0
		4'h1: seg_led = {seg_dot,7'h06};  //  1
		4'h2: seg_led = {seg_dot,7'h5b};  //  2
		4'h3: seg_led = {seg_dot,7'h4f};  //  3
		4'h4: seg_led = {seg_dot,7'h66};  //  4
		4'h5: seg_led = {seg_dot,7'h6d};  //  5
		4'h6: seg_led = {seg_dot,7'h7d};  //  6
		4'h7: seg_led = {seg_dot,7'h07};  //  7
		4'h8: seg_led = {seg_dot,7'h7f};  //  8
		4'h9: seg_led = {seg_dot,7'h6f};  //  9
		4'ha: seg_led = {seg_dot,7'h77};  //  A
		4'hb: seg_led = {seg_dot,7'h7C};  //  b
		4'hc: seg_led = {seg_dot,7'h39};  //  C
		4'hd: seg_led = {seg_dot,7'h5e};  //  d
		4'he: seg_led = {seg_dot,7'h79};  //  E
		4'hf: seg_led = {seg_dot,7'h71};  //  F
		default: seg_led = {seg_dot,7'h00};
	endcase

assign seg_sel = 1'b0;	//锟斤拷锟斤拷锟斤拷锟斤拷使锟斤拷

endmodule

 

（4）温度传感器模块,该模块采用单总线协议,读取ds18b20温度值,然后通过oled显示,。该模块包含:输入信号clk(为模块提供时钟信号),res_n(低电平复位信号),one_wire (ds18b20引脚控制),data_out(adc转换后电压值暂存寄存器)

module DS18B20Z
(
	input				clk,			// system clock
	input				rst_n,			// system reset, active low
	inout				one_wire,		// ds18b20z one-wire-bus
	output	reg	[15:0]	data_out		// ds18b20z data_out
);

	localparam	IDLE	=	3'd0;
	localparam	MAIN	=	3'd1;
	localparam	INIT	=	3'd2;
	localparam	WRITE	=	3'd3;
	localparam	READ	=	3'd4;
	localparam	DELAY	=	3'd5;

	// generate clk_1mhz clock
	reg					clk_1mhz;
	reg		[2:0]		cnt_1mhz;
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt_1mhz <= 3'd0;
			clk_1mhz <= 1'b0;
		end else if(cnt_1mhz >= 3'd5) begin
			cnt_1mhz <= 3'd0;
			clk_1mhz <= ~clk_1mhz;
		end else begin
			cnt_1mhz <= cnt_1mhz + 1'b1;
		end
	end

	reg					one_wire_buffer;
	reg		[3:0]		cnt_main;
	reg		[7:0]		data_wr;
	reg		[7:0]		data_wr_buffer;
	reg		[2:0]		cnt_init;
	reg		[19:0]		cnt_delay;
	reg		[19:0]		num_delay;
	reg		[5:0]		cnt_write;
	reg		[5:0]		cnt_read;
	reg		[15:0]		temperature;
	reg		[7:0]		temperature_buffer;
	reg		[2:0] 		state = IDLE;
	reg		[2:0] 		state_back = IDLE;
	// always@(posedge clk or negedge rst_n) begin
	always@(posedge clk_1mhz or negedge rst_n) begin
		if(!rst_n) begin
			state <= IDLE;
			state_back <= IDLE;
			cnt_main <= 4'd0;
			cnt_init <= 3'd0;
			cnt_write <= 6'd0;
			cnt_read <= 6'd0;
			cnt_delay <= 20'd0;
			one_wire_buffer <= 1'bz;
			temperature <= 16'h0;
		end else begin
			case(state)
				IDLE:begin
						state <= MAIN;
						state_back <= MAIN;
						cnt_main <= 4'd0;
						cnt_init <= 3'd0;
						cnt_write <= 6'd0;
						cnt_read <= 6'd0;
						cnt_delay <= 20'd0;
						one_wire_buffer <= 1'bz;
					end
				MAIN:begin
						if(cnt_main >= 4'd11) cnt_main <= 1'b0;
						else cnt_main <= cnt_main + 1'b1;
						case(cnt_main)
							4'd0: begin state <= INIT; end
							4'd1: begin data_wr <= 8'hcc;state <= WRITE; end
							4'd2: begin data_wr <= 8'h44;state <= WRITE; end
							4'd3: begin num_delay <= 20'd750000;state <= DELAY;state_back <= MAIN; end

							4'd4: begin state <= INIT; end
							4'd5: begin data_wr <= 8'hcc;state <= WRITE; end
							4'd6: begin data_wr <= 8'hbe;state <= WRITE; end

							4'd7: begin state <= READ; end
							4'd8: begin temperature[7:0] <= temperature_buffer; end

							4'd9: begin state <= READ; end
							4'd10: begin temperature[15:8] <= temperature_buffer; end

							4'd11: begin state <= IDLE;data_out <= temperature; end
							default: state <= IDLE;
						endcase
					end
				INIT:begin
						if(cnt_init >= 3'd6) cnt_init <= 1'b0;
						else cnt_init <= cnt_init + 1'b1;
						case(cnt_init)
							3'd0: begin one_wire_buffer <= 1'b0; end
							3'd1: begin num_delay <= 20'd500;state <= DELAY;state_back <= INIT; end
							3'd2: begin one_wire_buffer <= 1'bz; end
							3'd3: begin num_delay <= 20'd100;state <= DELAY;state_back <= INIT; end
							3'd4: begin if(one_wire) state <= IDLE; else state <= INIT; end
							3'd5: begin num_delay <= 20'd400;state <= DELAY;state_back <= INIT; end
							3'd6: begin state <= MAIN; end
							default: state <= IDLE;
						endcase
					end
				WRITE:begin
						if(cnt_write >= 6'd50) cnt_write <= 1'b0;
						else cnt_write <= cnt_write + 1'b1;
						case(cnt_write)
							//lock data_wr
							6'd0: begin data_wr_buffer <= data_wr; end
							//write bit 0
							6'd1: begin one_wire_buffer <= 1'b0; end
							6'd2: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd3: begin one_wire_buffer <= data_wr_buffer[0]; end
							6'd4: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd5: begin one_wire_buffer <= 1'bz; end
							6'd6: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 1
							6'd7: begin one_wire_buffer <= 1'b0; end
							6'd8: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd9: begin one_wire_buffer <= data_wr_buffer[1]; end
							6'd10: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd11: begin one_wire_buffer <= 1'bz; end
							6'd12: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 2
							6'd13: begin one_wire_buffer <= 1'b0; end
							6'd14: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd15: begin one_wire_buffer <= data_wr_buffer[2]; end
							6'd16: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd17: begin one_wire_buffer <= 1'bz; end
							6'd18: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 3
							6'd19: begin one_wire_buffer <= 1'b0; end
							6'd20: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd21: begin one_wire_buffer <= data_wr_buffer[3]; end
							6'd22: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd23: begin one_wire_buffer <= 1'bz; end
							6'd24: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 4
							6'd25: begin one_wire_buffer <= 1'b0; end
							6'd26: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd27: begin one_wire_buffer <= data_wr_buffer[4]; end
							6'd28: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd29: begin one_wire_buffer <= 1'bz; end
							6'd30: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 5
							6'd31: begin one_wire_buffer <= 1'b0; end
							6'd32: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd33: begin one_wire_buffer <= data_wr_buffer[5]; end
							6'd34: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd35: begin one_wire_buffer <= 1'bz; end
							6'd36: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 6
							6'd37: begin one_wire_buffer <= 1'b0; end
							6'd38: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd39: begin one_wire_buffer <= data_wr_buffer[6]; end
							6'd40: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd41: begin one_wire_buffer <= 1'bz; end
							6'd42: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 7
							6'd43: begin one_wire_buffer <= 1'b0; end
							6'd44: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd45: begin one_wire_buffer <= data_wr_buffer[7]; end
							6'd46: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd47: begin one_wire_buffer <= 1'bz; end
							6'd48: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//back to main
							6'd49: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd50: begin state <= MAIN; end
							default: state <= IDLE;
						endcase
					end
				READ:begin
						if(cnt_read >= 6'd48) cnt_read <= 1'b0;
						else cnt_read <= cnt_read + 1'b1;
						case(cnt_read)
							//read bit 0
							6'd0: begin one_wire_buffer <= 1'b0; end
							6'd1: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd2: begin one_wire_buffer <= 1'bz; end
							6'd3: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd4: begin temperature_buffer[0] <= one_wire; end
							6'd5: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 1
							6'd6: begin one_wire_buffer <= 1'b0; end
							6'd7: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd8: begin one_wire_buffer <= 1'bz; end
							6'd9: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd10: begin temperature_buffer[1] <= one_wire; end
							6'd11: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 2
							6'd12: begin one_wire_buffer <= 1'b0; end
							6'd13: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd14: begin one_wire_buffer <= 1'bz; end
							6'd15: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd16: begin temperature_buffer[2] <= one_wire; end
							6'd17: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 3
							6'd18: begin one_wire_buffer <= 1'b0; end
							6'd19: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd20: begin one_wire_buffer <= 1'bz; end
							6'd21: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd22: begin temperature_buffer[3] <= one_wire; end
							6'd23: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 4
							6'd24: begin one_wire_buffer <= 1'b0; end
							6'd25: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd26: begin one_wire_buffer <= 1'bz; end
							6'd27: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd28: begin temperature_buffer[4] <= one_wire; end
							6'd29: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 5
							6'd30: begin one_wire_buffer <= 1'b0; end
							6'd31: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd32: begin one_wire_buffer <= 1'bz; end
							6'd33: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd34: begin temperature_buffer[5] <= one_wire; end
							6'd35: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 6
							6'd36: begin one_wire_buffer <= 1'b0; end
							6'd37: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd38: begin one_wire_buffer <= 1'bz; end
							6'd39: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd40: begin temperature_buffer[6] <= one_wire; end
							6'd41: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 7
							6'd42: begin one_wire_buffer <= 1'b0; end
							6'd43: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd44: begin one_wire_buffer <= 1'bz; end
							6'd45: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd46: begin temperature_buffer[7] <= one_wire; end
							6'd47: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//back to main
							6'd48: begin state <= MAIN; end
							default: state <= IDLE;
						endcase
					end
				DELAY:begin
						if(cnt_delay >= num_delay) begin
							cnt_delay <= 1'b0;
							state <= state_back;
						end else cnt_delay <= cnt_delay + 1'b1;
					end
			endcase
		end
	end

	assign	one_wire = one_wire_buffer;

endmodule

5、项目的功能

实现0-3.3V电压测量并通过oled实时显示。

6、遇到的问题

（1）在注册时注册码绑定网卡,由于电脑没有网口.采用usb转以太网模块,当以太网模块没有接入电脑,软件就不能使用。

（2）想完成综合项目,但不太理解dds具体工作原理,项目已完成锁相环倍频功能,查表法,奈何实力不允许,无法继续更多功能。

7、总结与展望

完成项目后有以下感悟：

  1. 本次比赛参考了不少电子森林优秀作品的程序,感谢电子森林提供的学习环境及机会,感谢电子森林老师的视频知道.
  2. VHDL和verilog各有优劣，其中verilog语法与c有些许相似之处，个人使用更加方便。但是语言仅仅只是一个工具，尤其在硬件设计里，代码写得漂不漂亮，并不重要，最关键的是设计思想
  3. 单片机c语言和FPGA编程完全是两种思路， fpga是并行运算,单片机是单线程运行,从大学开始玩单片机,到工作玩单片机,加起来块6年了,还是首次接触fpga,慢慢觉得fpga真的太强大了,仅仅12M主频,但72M的stm32是无法比拟的.
  4. 展望：在接下来的一段时间继续完善项目，增加新的功能,实现dds功能。
软硬件
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software.zip
团队介绍
本人为打工人，从事嵌入式行业4年之久，做过的项目有工业灯联网，实现码头，港口及公共场合智能照明，做过电动车防盗项目，实现电动车的定位，主要负责软件研发及硬件设计。大学学过fpga,时隔5年,再次使用FPGA开发板,
团队成员
杨满意
本人为打工人，从事嵌入式行业4年之久，做过的项目有工业灯联网，实现码头，港口及公共场合智能照明，做过电动车防盗项目，实现电动车的定位，主要负责软件研发及硬件设计。大学学过fpga,时隔5年,再次使用FPGA开发板,
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