一.实验要求

使用串行DAC AD5626设计一款任意波形发生器

搭配单片机或FPGA或其它方式的控制逻辑能够产生10Hz到20KHz范围内的正弦波信号

输出信号幅度要达到3Vpp，直流偏移可调1.5V到3.5V

使用套件中的Micro USB适配器通过USB给面包板供电，供电电压为5V

使用ADALP2000套件中的运算放大器搭建一个Sallen-Key滤波器，滤除40KHz以上的混叠信号，输出运算放大器也选自ADALP2000套件

二、实验原理

1. AD5626（DAC）AD5626属于nanoDAC®系列，是一款完整的串行输入、12位电压输出数模转换器(DAC)，采用5 V单电源供电。它集成了DAC、输入移位寄存器和锁存、基准电压源和一个轨到轨输出放大器。

1. AD5626可采用自然二进制以MSB优先加载方式编程。输出运算放大器摆幅可达到任一供电轨，且设置范围为0 V至4.095 V，分辨率为每位1 mV。它能提供5 mA的吸电流和源电流。

    

2. 引脚：

4.FPGA程序

module AD5626_driver
(
input				clk,		//系统时钟
input				rst_n,  	//系统复位，低有效

output	reg			dac_done,	//DAC采样完成标志
input		[11:0]	dac_data,	//DAC采样数据

output	reg			dac_sync,	//SPI总线CS
output	reg			dac_clk,	//SPI总线SCLK
output	reg			dac_dat,   //SPI总线MOSI
output	reg			dac_ldac	
);

localparam	HIGH = 1'b1;
localparam	LOW  = 1'b0;

reg [7:0] cnt;
always @(posedge clk or negedge rst_n)
	if(!rst_n) cnt <= 1'b0;
	else if(cnt >= 8'd28) cnt <= 1'b0;
	else cnt <= cnt + 1'b1;
	
reg [11:0] data;
always @(posedge clk or negedge rst_n)
	if(!rst_n) begin
		dac_sync <= HIGH; dac_clk <= LOW; dac_dat <= LOW;dac_ldac <= HIGH;
	end else case(cnt)
		8'd0 : begin dac_sync <= HIGH; dac_clk <= HIGH; data <= dac_data; dac_ldac <= HIGH;end
		8'd1,8'd3,8'd5,8'd7,8'd9,8'd11,8'd13,8'd15,
		8'd17,8'd19,8'd21,8'd23,
		8'd25: begin dac_sync <= LOW; dac_clk <= HIGH;dac_ldac <= HIGH; end
		8'd2 : begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[11]; end //11
		8'd4 : begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[10]; end //10
		8'd6 : begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[9]; end //9
		8'd8 : begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[8]; end //8
		8'd10: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[7]; end //7
		8'd12: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[6]; end //6
		8'd14: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[5]; end //5
		8'd16: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[4]; end //4
		8'd18: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[3]; end //3
		8'd20: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[2]; end //2
		8'd22: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[1]; end //1
		8'd24: begin dac_sync <= LOW; dac_clk <= LOW; dac_ldac <= HIGH;dac_dat <= data[0]; end //0
		8'd26: begin dac_sync <= HIGH; dac_clk <= HIGH; dac_done <= HIGH; end 
		8'd27: begin dac_sync <= HIGH; dac_clk <= HIGH; dac_done <= LOW;dac_ldac <= LOW; end 
		8'd28: begin dac_sync <= HIGH; dac_clk <= HIGH; dac_ldac <= HIGH; end 	
		default : begin dac_sync <= HIGH; dac_clk <= HIGH;  end
	endcase

endmodule

5.验证 ，AD5626 SDIN 输入数据0011 1111 1111，输出模拟电压1.007Vdc

ADALM2000测量AD5626的输出电压1.007Vdc，验证 AD5626_driver的FPGA代码正确

6. 小脚丫FPGA驱动AD5626产生10KHz到20KHz的正玄波，锯齿波，三角波，幅度4.096V

7.调整信号幅度3Vpp，设计直流偏移1.5-3.5。

8.Sallen-Key滤波器，滤除40KHz以上的混叠信号.

心得体会：通过这次信号发生器的设计，感觉这个设计好的电路搬到实际电路上还是有很多困难，主要是直流偏移量的设置，自动修改直流偏移量，比如说使用PWM实现。滤波器的实现，理论设计后实际电路参数的选择，感觉知识还是不踏实，需要再多看课程的视频。