项目/活动
电赛
课堂
文档笔记
仿真/工具
参考设计
AI助手
发布项目
登录
/
注册
首页
>
文档笔记
>
工具
>
PCB设计
一些开源或免费的EDA工具
收藏
分享
脑图
一些开源或开源的EDA工具
系统
PandA-bambu – framework for research in high-level synthesis and HW/SW co-design
QElectroTech – Electronic diagrams
WaveDrom – draws your Timing Diagram or Waveform from simple textual description
HDL/FPGA设计相关
qucs (Quite Universal Circuit Simulator)
混合信号仿真、Verilog + VHDL
Icarus Verilog
数字电路的仿真和综合
Verilator
Verilog仿真和综合
ghdl
VHDL仿真工具
ChipVault
VHDL和Verilog RTL编译和综合
GTKwave
混合信号的波形查看
Electric
从HDL到布局布线等比较完整的设计工具
myHDL
用Python学习HDL
Edit code
在浏览器里面编辑、综合、仿真HDL代码
EPWave
基于浏览器的免费交互波形查看器
Yosys
Verilog RTL综合的框架
Arachne-pnr
支持ICE40系列FPGA的布局布线工具
nextpnr
跟供应商没关,时序驱动的FPGA布局布线工具
IceStorm
针对iCE40 FPGA的分析和创建位流的工具
icestudio
基于iCEStorm的用于FPGA板的可视化编辑器
Migen
基于Python的FPGA硬件设计工具套装
FOEDAG – Framework Open EDA Gui
fpga-bitstream – Generate a generica or fabric dependent bitstream
OpenFPGA – framework that enables rapid prototyping of customizable FPGA architectures
Qflow – digital synthesis flow using Verilog or VHDL, targets Xilinx or Altera
Raptor – commercial FPGA flow for FPGA design, RapidSilicon
SymbiFlow – FPGA framework for tools, Verilog to bitstream
IC设计
Gwave
模拟信号的波形查看
LabPlot
模拟信号的波形查看
Alliance
用以设计大规模集成电路的完整的免费工具以及库
Magic
VLSI的电路布局布线
Toped
IC Layout编辑器
Netgen
模拟或混合信号的网表比较工具
Dragon
数字芯片设计的布局工具
Fairly Good Router (FGR)
数字电路的布线工具
Qrouter
数字电路的细节走线工具
OS-VVM
数字电路验证工具
Teal
数字电路验证工具
Jove
基于Java API的数字电路验证工具
SystemC
数字设计的库
Alliance/Coriolis – VHDL compiler, simulator, logic synthesizer, automatic place and route
Animate – Virtuoso schematic users can quickly see an automated analog layout, freemium tool from Pulsic
CflexHDL – design digital circuits in C, simulate really fast with a regular compiler.
Chisel – Hardware compiler framework
cocotb – coroutine based co-simulation testbench environment for verifying VHDL and SystemVerilog using Python
CUGR – Global routing tool developed by CUHK
CVC – Circuit Validity Checker, for errors in CDL netlist.
Edalize – Python library for interfacing EDA tools (Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus)
Fault – Design for Test
FuseSoc – package manager and a set of build tools for HDL code.
Gaw – Gtk Analog Wave viewer
GHDL – G HDL, a VHDL analyzer, compiler, simulator and synthesizer
Glade – Gds, Lef And Def Editor – layout and schematic editor, DRC, extraction, LVS.
Gnucap – GNU Circuit Analysis Package
Icarus Verilog – Verilog simulator (free)
ipyxact – Python based IP-XACT parser
IRSIM – switch-level simulator
KLayout – Mask layout tool
LibrEDA – place and route
LiteX – Migen/MiSoC based Core/SoC builder
Makerchip-app – Desktop connection to free online Makerchip IDE
Migen – Python toolbox for HDL design
MyHDL – Python as a hardware description and verification language
Netgen – Layout Versus Schematic (LVS) tool
nMigen – Python based HDL design
Ngspice – SPICE circuit simulation
OpenRAM – Memory compiler development framework
OpenROAD – RTL to GDS in 24 hours, no human in the loop
OpenSTA – Static Timing Analyzer
Oregano – schematic capture and SPICE circuit simulation
OSVVM – A VHDL verification framework, utility library, verification component library, and a simulator independent scripting flow
PipelineC – HLS using C
Qrouter – multi-level, over-the-cell maze router
Qucs – Quite Universal Circuit Simulator
RePlAce – global placement tool
Revolution EDA – Symbol and schematic editor, integration with Xyce for circuit simulation
SandPiper-SaaS – CLI connection to free (though proprietary) SandPiper™ microservice for TL-Verilog compilation.
SPEF-Extractor – A Python library that reads LEF and DEF files, extract RC parasitics then create a SPEF file
SpinalHDL – HDL that creates VHDL or Verilog
Verilator – Verilog simulator
WRspice – Circuit simulator.
XCircuit – Schematic capture for SPICE netlists and PostScript
XSCHEM – Schematic capture and netlisting: VHDL, Verilog, SPICE.
Xic – Schematic capture and IC layout editor.
Xyce – Parallel analog circuit simulator from Sandia National Laboratories
Yosys – Verilog RTL synthesis
PCB/电路设计相关
Electric
IC设计,有原理图、布局布线、LVS以及PCB布线
Xcircuit
支持原理图设计
Horizon EDA
原理图和PCB布局布线
Ktechlab
原理图绘制和仿真,以及微控制器的编程开发
LibrePCB
PCB布局布线
gnucap
通用电路仿真工具
LTSpice
SPICE仿真、原理图、波形查看、模拟器件
ngspice
混合信号的电路仿真
IRSIM
电路仿真
gEDA Suite
完整的EDA设计工具 - 电路设计、原理图输入、模拟数字仿真、原型及生产
PCB
电路板布局布线工具
pcb-rnd
PCB layout
FreePCB
PCB编辑器
Fritzing
针对创客等非专业人士的面包板、原理图和PCB设计
KiCad
完整强大的PCB设计工具
OMNeT++
电子系统层面(尤其是通信网络)的仿真环境
评论
0 / 100
发表评论
查看更多
硬禾发布
2022-12-11
8216
开源
EDA
硬禾服务号
关注最新动态
0512-67862536
info@eetree.cn
江苏省苏州市苏州工业园区新平街388号腾飞创新园A2幢815室
苏州硬禾信息科技有限公司
友情链接
STEP小脚丫
纳芯微电子
Copyright © 2024 苏州硬禾信息科技有限公司 All Rights Reserved 苏ICP备19040198号