140 analog nodes (internal and external - see note below)
360 digital nodes
720 digital ports
300 digital components
360 digital outputs
SIMPLIS仿真(电路的大小受限)
A total of no more than 15 state variables. A capacitor or an inductor each requires one state variable. Each time-varying or small-signal AC source requires one state variable, with the exception of SINusoidal or COSinusoidal sources, which require two state variables per source.
A total of no more than 10 capacitors or inductors combined.
A total of no more than six switches, simple or transistor.
A total of no more than six logic gates.
A total of no more than 26 "states." Each PWL element requires one state. Each switch requires one state. Each time-varying source requires one state. Each logic gate requires one state.
A total of no more than 100 new topologies. 100 topologies will be enough for simple switching circuits that use simple models only. More complex circuits or circuits that have more complicated models may exceed this limit